Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
•In-System Reprogrammable™ (ISR™) CMOS CPLDs—JTAG interface for reconfigurability—Design changes do not cause pinout changes—Design changes do not cause timing changes•High density
—32 to 512 macrocells—32 to 2 I/O pins
—Five dedicated inputs including four clock pins•Simple timing model—No fanout delays—No expander delays
—No dedicated vs. I/O pin delays—No additional delay through PIM
—No penalty for using full 16 product terms••••
—No delay for steering or sharing product terms3.3V and 5V versionsPCI-compatible[1]
Programmable bus-hold capabilities on all I/Os Intelligent product term allocator provides:—0 to 16 product terms to any macrocell—Product term steering on an individual basis—Product term sharing among local macrocells•Flexible clocking
—Four synchronous clocks per device —Product term clocking
—Clock polarity control per logic block
•Consistent package/pinout offering across all densities—Simplifies design migration—Same pinout for 3.3V and 5.0V devices•Packages
—44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages
General Description
The Ultra37000™ family of CMOS CPLDs provides a range ofhigh-density programmable logic solutions with unparalleledsystem performance. The Ultra37000 family is designed tobring the flexibility, ease of use, and performance of the 22V10to high-density CPLDs. The architecture is based on a numberof logic blocks that are connected by a Programmable Inter-connect Matrix (PIM). Each logic block features its ownproduct term array, product term allocator, and 16 macrocells.The PIM distributes signals from the logic block outputs and allinput pins to the logic block inputs.
All of the Ultra37000 devices are electrically erasable and In-System Reprogrammable (ISR), which simplifies both designand manufacturing flows, thereby reducing costs. The ISRfeature provides the ability to reconfigure the devices withouthaving design changes cause pinout or timing changes. TheCypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out throughthe TDI and TDO pins, respectively. Because of the superiorroutability and simple timing model of the Ultra37000 devices,ISR allows users to change existing logic designs while simul-taneously fixing pinout assignments and maintaining systemperformance.
The entire family features JTAG for ISR and boundary scan,and is compatible with the PCI Local Bus specification,meeting the electrical and timing requirements. TheUltra37000 family features user programmable bus-holdcapabilities on all I/Os.Ultra37000 5.0V Devices
The Ultra37000 devices operate with a 5V supply and cansupport 5V or 3.3V I/O levels. VCCO connections provide thecapability of interfacing to either a 5V or 3.3V bus. Byconnecting the VCCO pins to 5V the user insures 5V TTL levelson the outputs. If VCCO is connected to 3.3V the output levelsmeet 3.3V JEDEC standard CMOS levels and are 5V tolerant.These devices require 5V ISR programming.Ultra37000V 3.3V Devices
Devices operating with a 3.3V supply require 3.3V on all VCCOpins, reducing the device’s power consumption. Thesedevices support 3.3V JEDEC standard CMOS output levels,and are 5V-tolerant. These devices allow 3.3V ISRprogramming.
Note:
1.Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to VCC, PCI VIH = 2V.
CypressSemiconductorCorporationDocument #: 38-03007 Rev. *C
•3901NorthFirstStreet•
SanJose,CA 95134
•408-943-2600 Revised July 7, 2003
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Selection Guide
5.0V Selection GuideGeneral Information
DeviceCY37032CY370CY37128CY37192CY37256CY37384CY37512Speed Bins
DeviceCY37032CY370CY37128CY37192CY37384CY37512
Device-Package Offering and I/O Count
DeviceCY37032CY370CY37128CY37192CY37256CY37384CY37512
Ultra37000 CPLD Family
Macrocells
32128192256384512
Dedicated Inputs
5555555
I/O Pins3232//128120128/160/192160/192160/192/2
Speed (tPD)
666.57.57.51010
Speed (fMAX)
200200167154154118118
200XX
167154XX
143125XXX
1008366
X
X
X
XXX
X
X
XXXX
CY37256 X44-LeadTQFP3737
44-LeadPLCC3737
44-LeadCLCC37
84-LeadPLCC6969
84-LeadCLCC100-LeadTQFP69
160-LeadTQFP160-LeadCQFP208-LeadPQFP208-LeadCQFP256-LeadBGA352-LeadBGA
6969133125133
133
165165165
165
197197197
269
3.3V Selection GuideGeneral Information
DeviceCY37032VCY370VCY37128VCY37192VCY37256VCY37384VCY37512V
Macrocells
32128192256384512
Dedicated Inputs
5555555
I/O Pins3232//80/128120128/160/192160/192160/192/2
Speed (tPD)
8.58.51012121515
Speed (fMAX)
1431431251001008383
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Ultra37000 CPLD Family
143XX
X
XX
XX
125
100XX
X
XXXX
83
66
Speed Bins
DeviceCY37032VCY370VCY37128VCY37192VCY37256VCY37384VCY37512V
Device-Package Offering & I/O Count
44-LeadTQFP44-LeadCLCC48-LeadFBGA84-LeadCLCC100-LeadTQFP100-LeadFBGA160-LeadTQFP160-LeadCQFP208-LeadPQFP208-LeadCQFP256-LeadBGA256-LeadFBGA352-LeadBGA3737
37
3737
69
6969
6985
133125133
133
165165165
Logic Block
The logic block is the basic building block of the Ultra37000architecture. It consists of a product term array, an intelligentproduct-term allocator, 16 macrocells, and a number of I/Ocells. The number of I/O cells varies depending on the deviceused. Refer to Figure1 for the block diagram.Product Term Array
Each logic block features a 72 x 87 programmable productterm array. This array accepts 36 inputs from the PIM, whichoriginate from macrocell feedbacks and device pins. ActiveLOW and active HIGH versions of each of these inputs aregenerated to create the full 72-input field. The 87 productterms in the array can be created from any of the 72 inputs. Of the 87 product terms, 80 are for general-purpose use forthe 16 macrocells in the logic block. Four of the remainingseven product terms in the logic block are output enable (OE)product terms. Each of the OE product terms controls up toeight of the 16 macrocells and is selectable on an individualmacrocell basis. In other words, each I/O cell can selectbetween one of two OE product terms to control the outputbuffer. The first two of these four OE product terms areavailable to the upper half of the I/O macrocells in a logic block.The other two OE product terms are available to the lower halfof the I/O macrocells in a logic block.
The next two product terms in each logic block are dedicatedasynchronous set and asynchronous reset product terms. Thefinal product term is the product term clock. The set, reset, OEand product term clock have polarity control to realize ORfunctions in a single pass through the array.
165
197197197
269
269
197
DeviceCY37032VCY370VCY37128VCY37192VCY37256VCY37384VCY37512V
400-LeadFBGA200
167
154
Architecture Overview of Ultra37000 Family
Programmable Interconnect Matrix
The PIM consists of a completely global routing matrix forsignals from I/O pins and feedbacks from the logic blocks. ThePIM provides extremely robust interconnection to avoid fittingand density limitations.
The inputs to the PIM consist of all I/O and dedicated input pinsand all macrocell feedbacks from within the logic blocks. Thenumber of PIM inputs increases with pin count and the numberof logic blocks. The outputs from the PIM are signals routed tothe appropriate logic blocks. Each logic block receives 36inputs from the PIM and their complements, allowing for 32-bitoperations to be implemented in a single pass through thedevice. The wide number of inputs to the logic block alsoimproves the routing capacity of the Ultra37000 family.An important feature of the PIM is its simple timing. The propa-gation delay through the PIM is accounted for in the timingspecifications for each device. There is no additional delay fortraveling through the PIM. In fact, all inputs travel through thePIM. As a result, there are no route-dependent timing param-eters on the Ultra37000 devices. The worst-case PIM delaysare incorporated in all appropriate Ultra37000 specifications. Routing signals through the PIM is completely invisible to theuser. All routing is accomplished by software—no hand routingis necessary. Warp and third-party development packagesautomatically route designs for the Ultra37000 family in amatter of minutes. Finally, the rich routing resources of theUltra37000 family accommodate last minute logic changeswhile maintaining fixed pin assignments.
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Ultra37000 CPLD Family
3
0−16
PRODUCTTERMS
2
I/OCELL0
2
MACRO-CELL0MACRO-CELL1
7
0−16
PRODUCTTERMS
tocells
2, 4, 6 8, 10, 12FROMPIM
36
72x87
PRODUCT TERM
ARRAY
80
PRODUCTTERMALLOCATOR
0−16
PRODUCTTERMS
MACRO-CELL14MACRO-CELL15
I/OCELL14
0−16
TOPIM
168
PRODUCTTERMS
Figure 1.Logic Block with 50% Buried Macrocells
Low-Power Option
Each logic block can operate in high-speed mode for criticalpath performance, or in low-power mode for power conser-vation. The logic block mode is set by the user on a logic blockby logic block basis. Product Term Allocator
Through the product term allocator, software automaticallydistributes product terms among the 16 macrocells in the logicblock as needed. A total of 80 product terms are available fromthe local product term array. The product term allocatorprovides two important capabilities without affecting perfor-mance: product term steering and product term sharing. Product Term Steering
Product term steering is the process of assigning productterms to macrocells as needed. For example, if one macrocellrequires ten product terms while another needs just three, theproduct term allocator will “steer” ten product terms to onemacrocell and three to the other. On Ultra37000 devices,product terms are steered on an individual basis. Any numberbetween 0 and 16 product terms can be steered to anymacrocell. Note that 0 product terms is useful in cases wherea particular macrocell is unused or used as an input register. Product Term Sharing
Product term sharing is the process of using the same productterm among multiple macrocells. For example, if more thanone output has one or more product terms in its equation thatare common to other outputs, those product terms are onlyprogrammed once. The Ultra37000 product term allocatorallows sharing across groups of four output macrocells in a
variable fashion. The software automatically takes advantageof this capability—the user does not have to intervene. Note that neither product term sharing nor product termsteering have any effect on the speed of the product. All worst-case steering and sharing configurations have been incorpo-rated in the timing specifications for the Ultra37000 devices.Ultra37000 Macrocell
Within each logic block there are 16 macrocells. Macrocellscan either be I/O Macrocells, which include an I/O Cell whichis associated with an I/O pin, or buried Macrocells, which donot connect to an I/O. The combination of I/O Macrocells andburied Macrocells varies from device to device.Buried Macrocell
Figure2 displays the architecture of buried macrocells. Theburied macrocell features a register that can be configured ascombinatorial, a D flip-flop, a T flip-flop, or a level-triggeredlatch.
The register can be asynchronously set or asynchronouslyreset at the logic block level with the separate set and resetproduct terms. Each of these product terms features program-mable polarity. This allows the registers to be set or resetbased on an AND expression or an OR expression.
Clocking of the register is very flexible. Four globalsynchronous clocks and a product term clock are available toclock the register. Furthermore, each clock features program-mable polarity so that registers can be triggered on falling aswell as rising edges (see the Clocking section). Clock polarityis chosen at the logic block level.
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The buried macrocell also supports input register capability.The buried macrocell can be configured to act as an inputregister (D-type or latch) whose input comes from the I/O pinassociated with the neighboring macrocell. The output of allburied macrocells is sent directly to the PIM regardless of itsconfiguration. I/O Macrocell
Figure2 illustrates the architecture of the I/O macrocell. TheI/O macrocell supports the same functions as the buriedmacrocell with the addition of I/O capability. At the output of themacrocell, a polarity control mux is available to select activeLOW or active HIGH signals. This has the added advantageof allowing significant logic reduction to occur in many appli-cations.
The Ultra37000 macrocell features a feedback path to the PIMseparate from the I/O pin input path. This means that if themacrocell is buried (fed back internally only), the associatedI/O pin can still be used as an input.
Document #: 38-03007 Rev. *CUltra37000 CPLD Family
Bus Hold Capabilities on all I/Os
Bus-hold, which is an improved version of the popular internalpull-up resistor, is a weak latch connected to the pin that doesnot degrade the device’s performance. As a latch, bus-holdmaintains the last state of a pin when the pin is placed in ahigh-impedance state, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unuseddevice pins to remain unconnected on the board, which isparticularly useful during prototyping as designers can routenew signals to the device without cutting trace connections toV“Understanding Bus-Hold — A Feature of Cypress CPLDs.”CC or GND. For more information, see the application noteProgrammable Slew Rate Control
Each output has a programmable configuration bit, which setsthe output slew rate to fast or slow. For designs concerned withmeeting FCC emissions standards the slow edge provides forlower system noise. For designs requiring very high perfor-mance the fast edge rate provides maximum system perfor-mance.
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Ultra37000 CPLD Family
I/O MACROCELL
FROM PTM
0−16PRODUCTTERMS
C25
01
FAST
SLEW
SLOW
0
PD/T/L
O
Q
1
01C4
DECODE
“0” “1”
0123
O
O
C26I/O CELL
4
0123
O
R
C0C1C24
10
C6C5
C2C3
BURIED MACROCELL
FROM PTM0−16
PRODUCTTERMS
C25
01
0
0123
1
Q
C70
O
PD/T/L
R
DECODEQ
1
O
4
C0C1C24
10
C2C3
FEEDBACK TO PIM
FEEDBACK TO PIMFEEDBACK TO PIM
ASYNCHRONOUSBLOCK RESET
4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)
ASYNCHRONOUS
1 ASYNCHRONOUS CLOCK(PTCLK)
BLOCK PRESET
OE0OE1
Figure 2.I/O and Buried Macrocells
INPUT PIN
0123
C12C13
OTO PIM
FROM CLOCKPOLARITY MUXES
0123C10C11
D
O
Q
D
Q
DLE
Q
Figure 3.Input Macrocell
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Ultra37000 CPLD Family
01
O
TO CLOCK MUX ON
ALL INPUT MACROCELLS
INPUT/CLOCK PIN
C12
0
O1
C13,C14,C15
O
TO PIM
ORC16
CLOCK POLARITY MUX ONE PER LOGIC BLOCKFOR EACH CLOCK INPUT
TO CLOCK MUX IN EACH
LOGIC BLOCK
FROM CLOCKPOLARITY INPUT
CLOCK PINS
0123C8C9
D
O
Q
D
Q
0123C10C11
DLE
Q
Figure 4.Input/Clock Macrocell
Clocking
Each I/O and buried macrocell has access to four synchronousclocks (CLK0, CLK1, CLK2 and CLK3) as well as anasynchronous product term clock PTCLK. Each inputmacrocell has access to all four synchronous clocks.Dedicated Inputs/Clocks
Five pins on each member of the Ultra37000 family are desig-nated as input-only. There are two types of dedicated inputson Ultra37000 devices: input pins and input/clock pins.Figure3 illustrates the architecture for input pins. Four inputoptions are available for the user: combinatorial, registered,double-registered, or latched. If a registered or latched optionis selected, any one of the input clocks can be selected forcontrol.
Figure4 illustrates the architecture for the input/clock pins.Like the input pins, input/clock pins can be combinatorial,registered, double-registered, or latched. In addition, thesepins feed the clocking structures throughout the device. Theclock path at the input has user-configurable polarity. Product Term Clocking
In addition to the four synchronous clocks, the Ultra37000family also has a product term clock for asynchronousclocking. Each logic block has an independent product termclock which is available to all 16 macrocells. Each product termclock also supports user configurable polarity selection.Timing Model
One of the most important features of the Ultra37000 family isthe simplicity of its timing. All delays are worst case andsystem performance is unaffected by the features used. Figure5 illustrates the true timing model for the 167-MHz devices inhigh speed mode. For combinatorial paths, any input to anyoutput incurs a 6.5-ns worst-case delay regardless of theamount of logic used. For synchronous systems, the input set-up time to the output macrocells for any input is 3.5 ns and theclock to output time is also 4.0 ns. These measurements arefor any output and synchronous clock, regardless of the logicused.
INPUT
The Ultra37000 features:•No fanout delays•No expander delays
•No dedicated vs. I/O pin delays•No additional delay through PIM
•No penalty for using 0–16 product terms•No added delay for steering product terms•No added delay for sharing product terms•No routing delays
•No output bypass delays
The simple timing model of the Ultra37000 family eliminatesunexpected performance penalties.
COMBINATORIAL SIGNAL
INPUT
tPD = 6.5 nsREGISTERED SIGNAL
tS = 3.5 ns
D,T,L
O
OUTPUT
tCO = 4.5 ns
OUTPUT
CLOCK
Figure 5.Timing Model for CY37128
JTAG and PCI Standards
PCI Compliance
5V operation of the Ultra37000 is fully compliant with the PCILocal Bus Specification published by the PCI Special InterestGroup. The 3.3V products meet all PCI requirements exceptfor the output 3.3V clamp, which is in direct conflict with 5Vtolerance. The Ultra37000 family’s simple and predictabletiming model ensures compliance with the PCI AC specifica-tions independent of the design.
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IEEE 1149.1-compliant JTAG
The Ultra37000 family has an IEEE 1149.1 JTAG interface forboth Boundary Scan and ISR.Boundary Scan
The Ultra37000 family supports Bypass, Sample/Preload,Extest, Idcode, and Usercode boundary scan instructions. TheJTAG interface is shown in Figure6.
Instruction Register
TDI
TDO
TMSJTAGBypass Reg.CONTROLLER
TAP
TCK
Boundary ScanidcodeUsercodeISR Prog.
Data Registers
Figure 6.JTAG Interface
In-System Reprogramming (ISR)
In-System Reprogramming is the combination of the capabilityto program or reprogram a device on-board, and the ability tosupport design changes without changing the system timingor device pinout. This combination means design changesduring debug or field upgrades do not cause board respins.The Ultra37000 family implements ISR by providing a JTAGcompliant interface for on-board programming, robust routingresources for pinout flexibility, and a simple timing model forconsistent system performance.
Development Software Support
Warp
Warp is a state-of-the-art compiler and complete CPLD designtool. For design entry, Warp provides an IEEE-STD-1076/11VHDL text editor, an IEEE-STD-13 Verilog text editor, and agraphical finite state machine editor. It provides optimizedsynthesis and fitting by replacing basic circuits with ones pre-optimized for the target device, by implementing logic inunused memory and by perfect communication between fittingand synthesis. To facilitate design and debugging, Warpprovides graphical timing simulation and analysis. Warp Professional™
Warp Professional contains several additional features. Itprovides an extra method of design entry with its graphicalblock diagram editor. It allows up to 5 ms timing simulationinstead of only 2 ms. It allows comparison of waveforms beforeand after design changes.
Document #: 38-03007 Rev. *CUltra37000 CPLD Family
Warp Enterprise™
Warp Enterprise provides even more features. It providesunlimited timing simulation and source-level behavioralsimulation as well as a debugger. It has the ability to generategraphical HDL blocks from HDL text. It can even generatetestbenches.
Warp is available for PC and UNIX platforms. Some featuresare not available in the UNIX version. For further informationsee the Warp for PC, Warp for UNIX, Warp Professional andWarp Enterprise data sheets on Cypress’s web site(www.cypress.com).Third-Party Software
Although Warp is a complete CPLD development tool on itsown, it interfaces with nearly every third party EDA tool. Allmajor third-party software vendors provide support for theUltra37000 family of devices. Refer to the third-party softwaredata sheet or contact your local sales office for a list ofcurrently supported third-party vendors.Programming
There are four programming options available for Ultra37000devices. The first method is to use a PC with the 37000UltraISR programming cable and software. With this method,the ISR pins of the Ultra37000 devices are routed to aconnector at the edge of the printed circuit board. The 37000UltraISR programming cable is then connected between theparallel port of the PC and this connector. A simple configu-ration file instructs the ISR software of the programmingoperations to be performed on each of the Ultra37000 devicesin the system. The ISR software then automatically completesall of the necessary data manipulations required to accomplishthe programming, reading, verifying, and other ISR functions.For more information on the Cypress ISR Interface, see theISR Programming Kit data sheet (CY3700i).
The second method for programming Ultra37000 devices is onautomatic test equipment (ATE). This is accomplished througha file created by the ISR software. Check the Cypress websitefor the latest ISR software download information.
The third programming option for Ultra37000 devices is toutilize the embedded controller or processor that alreadyexists in the system. The Ultra37000 ISR software assists inthis method by converting the device JEDEC maps into theISR serial stream that contains the ISR instruction informationand the addresses and data of locations to be programmed.The embedded controller then simply directs this ISR streamto the chain of Ultra37000 devices to complete the desiredreconfiguring or diagnostic operations. Contact your localsales office for information on availability of this option.The fourth method for programming Ultra37000 devices is touse the same programmer that is currently being used toprogram FLASH370i devices.
For all pinout, electrical, and timing requirements, refer todevice data sheets. For ISR cable and software specifications,refer to the UltraISR kit data sheet (CY3700i). Third-Party Programmers
As with development software, Cypress support is availableon a wide variety of third-party programmers. All major third-party programmers (including BP Micro, Data I/O, and SMS)support the Ultra37000 family.
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Logic Block Diagrams
CY37032/CY37032V
Clock/InputInput14
Ultra37000 CPLD Family
TDITCKTMS
JTAG TapController
TDO
4
16 I/OsI/O0−I/O15
LOGICBLOCKA
16
36163
JTAGEN
16 I/OsI/O16−I/O31
PIM
16LOGICBLOCKB16
CY370/CY370V (100-Lead TQFP)
Input
Clock/Input
14
4
36
16 I/Os
I/O0-I/O15
LOGICBLOCKALOGICBLOCKB
163616361LOGICBLOCKDLOGICBLOCKC
16 I/Os
I/O48-I/O63
PIM
36
16 I/Os
I/O32-I/O47
16
16 I/Os
I/O16-I/O31
32
TDITCKTMS
JTAG TapControllerTDO
32
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Logic Block Diagrams (continued)
CY37128/CY37128V (160-lead TQFP)
Ultra37000 CPLD Family
TDI
CLOCK
INPUTSINPUTS1
INPUT
MACROCELL4
4
INPUT/CLOCKMACROCELLS
436
PIM
16361636163616LOGICBLOCK
TCKTMS
JTAG TapController
TDO
JTAGEN
I/O0–I/O15
16 I/Os
LOGICBLOCK
A
361636163616361616 I/Os
I/O112–I/O127
H
I/O16–I/O31
16 I/Os
LOGICBLOCK
B
LOGICBLOCK
16 I/OsG
I/O96–I/O111
16 I/Os
I/O32–I/O47
LOGICBLOCK
C
LOGICBLOCK
16 I/Os
I/O80–I/O95
16 I/Os
I/O–I/O79
F
I/O28–I/O63
16 I/OsLOGICBLOCK
D
LOGICBLOCK
E
Clock/InputInput14CY37192/CY37192V (160-lead TQFP)
410 I/OsI/O0–I/O910 I/OsI/O10–I/O1910 I/OsI/O20–I/O29I/O30–I/O39I/O40–I/O4910 I/OsI/O50–I/O59 10 I/OsLOGICBLOCKALOGICBLOCKBLOGICBLOCKCLOGICBLOCKDLOGICBLOCKELOGICBLOCKF6036163616361636163616361636163616361LOGICBLOCKLLOGICBLOCKKLOGICBLOCKJLOGICBLOCKILOGICBLOCKHLOGICBLOCKG6010 I/OsI/O110–I/O11910 I/OsI/O100–I/O10910 I/OsI/O90–I/O9910 I/OsI/O80–I/O10 I/OsI/O70–I/O7910 I/OsI/O60–I/O69PIM36163616361610 I/OsTDITCKTMS
JTAG TapController
TDO
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Logic Block Diagrams (continued)
CY37256/CY37256V (256-lead BGA)
Clock/InputInput14
Ultra37000 CPLD Family
4
12 I/OsI/O0−I/O11
12 I/Os
I/O12−I/O23
12 I/Os
I/O24−I/O35I/O36−I/O47I/O48−I/O59
12 I/Os
I/O60−I/O71I/O72−I/O83
12 I/Os12 I/Os
LOGICBLOCKALOGICBLOCKBLOGICBLOCKCLOGICBLOCKDLOGICBLOCKELOGICBLOCKFLOGICBLOCKGLOGICBLOCKH
96
36163616361636163616361636163616361636163616361LOGICBLOCKPLOGICBLOCKOLOGICBLOCKNLOGICBLOCKMLOGICBLOCKLLOGICBLOCKKLOGICBLOCKJLOGICBLOCK
I96
12 I/OsI/O180−I/O19112 I/Os
I/O168−I/O17912 I/Os
I/O156−I/O16712 I/Os
I/O144−I/O15512 I/Os
I/O132−I/O14312 I/Os
I/O120−I/O13112 I/Os
I/O108−I/O11912 I/Os
I/O96−I/O107
12 I/Os
PIM
361636163616361612 I/Os
I/O84−I/O95
TDITCKTMS
JTAG TapController
TDO
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Logic Block Diagrams (continued)
CY37384/CY37384V (256-Lead BGA)Clock/InputInput14
Ultra37000 CPLD Family
4
12 I/OsI/O0−I/O11
12 I/Os
I/O12−I/O23
12 I/Os
I/O24−I/O35
LOGICBLOCKAALOGICBLOCKABLOGICBLOCKACLOGICBLOCKAD
12 I/Os
I/O36−I/O47
LOGICBLOCKAELOGICBLOCKAF
12 I/Os
I/O48−I/O59I/O60−I/O71
12 I/Os
LOGICBLOCKAGLOGICBLOCKAHLOGICBLOCKAILOGICBLOCKAJ
12 I/Os
I/O84−I/O95
LOGICBLOCKAKLOGICBLOCKAL
TDITCKTMS
361636163616361636163616361636163616361636163616361636163616361LOGICBLOCKBLLOGICBLOCKBKLOGICBLOCKBJLOGICBLOCKBILOGICBLOCKBHLOGICBLOCKBGLOGICBLOCKBFLOGICBLOCKBELOGICBLOCKBDLOGICBLOCKBCLOGICBLOCKBBLOGICBLOCKBA
12 I/Os
I/O96−I/O10712 I/Os
I/O120−I/O14312 I/Os
I/O108−I/O13112 I/Os
I/O96−I/O11912 I/Os
I/O132−I/O15512 I/Os
I/O168−I/O19112 I/Os
I/O156−I/O17912 I/Os
I/O144−I/O167
PIM
3616361636163616361612 I/Os
I/O72−I/O83
361636163616JTAG TapController
TDO
9696Document #: 38-03007 Rev. *CPage 12 of 62
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Logic Block Diagrams (continued)
CY37512/CY37512V (352-Lead BGA)
InputClock/Input14Ultra37000 CPLD Family
412 I/OsI/O0−I/O1112 I/OsI/O12−I/O2312 I/OsI/O24−I/O35LOGICBLOCKAALOGICBLOCKABLOGICBLOCKACLOGICBLOCKADI/O36−I/O4712 I/OsLOGICBLOCKAELOGICBLOCKAF12 I/OsI/O48−I/O59LOGICBLOCKAGLOGICBLOCKAH12 I/OsI/O60−I/O71LOGICBLOCKAILOGICBLOCKAJI/O72−I/O8312 I/OsLOGICBLOCKAKLOGICBLOCKALLOGICBLOCKAMLOGICBLOCKANLOGICBLOCKAOLOGICBLOCKAP132TDITCKTMSJTAG TapControllerTDO36163616361636163616361636163616361636163616361636163616361636163616361636163616361636163616361LOGICBLOCKBPLOGICBLOCKBOLOGICBLOCKBNLOGICBLOCKBMLOGICBLOCKBLLOGICBLOCKBKLOGICBLOCKBJLOGICBLOCKBILOGICBLOCKBHLOGICBLOCKBGLOGICBLOCKBFLOGICBLOCKBELOGICBLOCKBDLOGICBLOCKBCLOGICBLOCKBBLOGICBLOCKBA13212 I/OsI/O180−I/O19112 I/OsI/O168−I/O17912 I/OsI/O156−I/O16712 I/OsI/O144−I/O15512 I/OsI/O132−I/O14312 I/OsI/O192−I/O20312 I/OsI/O204−I/O21512 I/OsI/O216−I/O22712 I/OsI/O252−I/O26312 I/OsI/O240−I/O25112 I/OsI/O228−I/O239PIM3616361636163616361636163616361612 I/OsI/O84−I/O9512 I/OsI/O96−I/O10712 I/OsI/O108−I/O11912 I/OsI/O120−I/O131Document #: 38-03007 Rev. *CPage 13 of 62
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5.0V Device CharacteristicsMaximum Ratings
(Above which the useful life may be impaired. For user guide-lines, not tested.)
Storage Temperature .................................–65°C to +150°CAmbient Temperature with
Power Applied.............................................–55°C to +125°CSupply Voltage to Ground Potential...............–0.5V to +7.0V
Ultra37000 CPLD Family
DC Voltage Applied to Outputs
in High-Z State................................................–0.5V to +7.0VDC Input Voltage............................................–0.5V to +7.0VDC Program Voltage.............................................4.5 to 5.5VCurrent into Outputs....................................................16 mAStatic Discharge Voltage...........................................> 2001V(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range[2]
RangeCommercialIndustrialMilitary[3]AmbientTemperature[2]0°C to +70°C –40°C to +85°C –55°C to +125°C
Junction Temperature0°C to +90°C –40°C to +105°C –55°C to +130°C
Output Condition
5V3.3V5V3.3V5V3.3V
VCC5V ± 0.25V5V ± 0.25V5V ± 0.5V5V ± 0.5V5V ± 0.5V5V ± 0.5V
VCCO5V ± 0.25V3.3V ± 0.3V5V ± 0.5V3.3V ± 0.3V5V ± 0.5V3.3V ± 0.3V
5.0V Device Electrical Characteristics Over the Operating Range
ParameterVOHVOHZ
Description
Output HIGH VoltageOutput HIGH Voltage with Output Disabled[5]
VCC = Min.VCC = Max.
Test Conditions
IOH = –3.2 mA (Com’l/Ind)[4]IOH = –2.0 mA (Mil)[4]IOH = 0 µA (Com’l)[6]IOH = 0 µA (Ind/Mil)[6]IOH = –100 µA (Com’l)[6]IOH = –150 µA (Ind/Mil)[6]IOL = 16 mA (Com’l/Ind)[4]IOL = 12 mA (Mil)[4][7]Min.Typ.2.42.4
4.24.53.63.60.50.5
2.0–0.5–10–50–30+75–75
+500–500VCCmax0.81050–160Max.
UnitVVVVVVVVVVµAµAmAµAµAµAµA
VOLVIHVILIIXIOZIOSIBHLIBHHIBHLOIBHHO
Output LOW VoltageInput HIGH VoltageInput LOW VoltageInput Load CurrentOutput Leakage CurrentInput Bus-Hold LOW Sustaining CurrentInput Bus-Hold HIGH Sustaining CurrentInput Bus-Hold LOW Overdrive CurrentInput Bus-Hold HIGH Overdrive Current
VCC = Min.
Guaranteed Input Logical HIGH Voltage for all InputsVI = GND OR VCC, Bus-Hold Disabled
Guaranteed Input Logical LOW Voltage for all Inputs[7]VO = GND or VCC, Output Disabled, Bus-Hold DisabledVCC = Min., VIL = 0.8VVCC = Min., VIH = 2.0VVCC = Max.VCC = Max.
Output Short Circuit Current[8, 5]VCC = Max., VOUT = 0.5V
Notes:
2.Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the
Ultra37000 Family devices, please refer to the Application Note titled “An Introduction to In System Reprogramming with the Ultra37000.”3.TA is the “Instant On” case temperature.4.IOH = –2 mA, IOL = 2 mA for TDO.
5.Tested initially and after any design or process changes that may affect these parameters.
6.When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled
during ISR programming. Refer to the application note “Understanding Bus-Hold” for additional information.
7.These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
8.Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
Document #: 38-03007 Rev. *CPage 14 of 62
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Inductance[5]
ParameterL
DescriptionMaximum PinInductance
Test ConditionsVIN = 5.0V at f = 1 MHz
44-LeadTQFP2
44-LeadPLCC5
44-LeadCLCC2
84-LeadPLCC8
Ultra37000 CPLD Family
84-LeadCLCC5
100-LeadTQFP8
160-LeadTQFP9
208-LeadPQFP11
UnitnH
Capacitance[5]
ParameterCI/OCCLKCDP
Description
Input/Output CapacitanceClock Signal CapacitanceDual Function Pins[9]Test Conditions
VIN = 5.0V at f = 1 MHz at TA = 25°CVIN = 5.0V at f = 1 MHz at TA = 25°CVIN = 5.0V at f = 1 MHz at TA = 25°C
Max.101216
UnitpFpFpF
Endurance Characteristics[5]
ParameterN
Description
Minimum Reprogramming Cycles
Test Conditions
Normal Programming Conditions[2]Min.1,000
Typ.10,000
UnitCycles
3.3V Device CharacteristicsMaximum Ratings
(Above which the useful life may be impaired. For user guide-lines, not tested.)
Storage Temperature .................................–65°C to +150°CAmbient Temperature with
Power Applied.............................................–55°C to +125°CSupply Voltage to Ground Potential...............–0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State................................................–0.5V to +7.0VDC Input Voltage............................................–0.5V to +7.0VDC Program Voltage.............................................3.0 to 3.6VCurrent into Outputs......................................................8 mAStatic Discharge Voltage............................................>2001V(per MIL-STD-883, Method 3015)
Latch-up Current......................................................>200 mA
Operating Range[2]
Range
CommercialIndustrialMilitary[3]Ambient Temperature[2]0°C to +70°C–40°C to +85°C–55°C to +125°C
Junction Temperature
0°C to +90°C–40°C to +105°C–55°C to +130°C
VCC[10]3.3V ± 0.3V3.3V ± 0.3V3.3V ± 0.3V
3.3V Device Electrical Characteristics Over the Operating Range
ParameterVOHVOLVIHVILIIXIOZIOSIBHL
Description
Output HIGH VoltageOutput LOW VoltageInput HIGH VoltageInput LOW VoltageInput Load CurrentOutput Leakage CurrentOutput Short Circuit Current[8, 5]Input Bus-Hold LOW Sustaining Current
VCC = Min.VCC = Min.
Test ConditionsIOH = –4 mA (Com’l)[4]IOH = –3 mA (Mil)[4]IOL = 8 mA (Com’l)[4]IOL = 6 mA (Mil)[4]Guaranteed Input Logical HIGH Voltage for all Inputs[7]
Guaranteed Input Logical LOW Voltage for all Inputs[7]
VI = GND OR VCC, Bus-Hold DisabledVO = GND or VCC, Output Disabled, Bus-Hold Disabled
VCC = Max., VOUT = 0.5VVCC = Min., VIL = 0.8V
2.0–0.5–10–50–30+75
5.50.81050–160
VVµAµAmAµA
0.5
V
Min.2.4
Max.
UnitV
Notes:
9.Dual pins are I/O with JTAG pins.
10.For CY370VP100-143AC, CY370VP100-143BBC, CY370VP44-143AC, CY370VP48-143BAC; Operating Range: VCC is 3.3V± 0.16V.
Document #: 38-03007 Rev. *CPage 15 of 62
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Ultra37000 CPLD Family
Test Conditions
VCC = Min., VIH = 2.0VVCC = Max.VCC = Max.
Min.–75
+500–500Max.
UnitµAµAµA
3.3V Device Electrical Characteristics Over the Operating Range (continued)
ParameterIBHHIBHLOIBHHO
Description
Input Bus-Hold HIGH Sustaining Current
Input Bus-Hold LOW Overdrive Current
Input Bus-Hold HIGH Overdrive Current
Inductance[5]
ParameterL
DescriptionMaximum PinInductance
Test ConditionsVIN = 3.3V at f = 1 MHz
44-LeadTQFP2
44-LeadPLCC5
44-LeadCLCC2
84-LeadPLCC8
84-LeadCLCC5
100-LeadTQFP8
160-LeadTQFP9
208-LeadPQFP11
UnitnH
Capacitance[5]
ParameterCI/OCCLKCDP
Description
Input/Output CapacitanceClock Signal CapacitanceDual Functional Pins[9]Test Conditions
VIN = 3.3V at f = 1 MHz at TA = 25°CVIN = 3.3V at f = 1 MHz at TA = 25°CVIN = 3.3V at f = 1 MHz at TA = 25°C
Max.81216
UnitpFpFpF
Endurance Characteristics[5]
ParameterN
Description
Minimum Reprogramming Cycles
Test Conditions
Normal Programming Conditions[2]Min.1,000
Typ.10,000
UnitCycles
AC Characteristics
5.0V AC Test Loads and Waveforms
5VOUTPUT
35 pF
INCLUDINGJIG ANDSCOPE
238Ω(COM’L)319Ω(MIL)
238Ω(COM'L)319Ω(MIL)
5VOUTPUT
5 pF
INCLUDINGJIG ANDSCOPE
3.0V
170Ω(COM'L)
GND236Ω(MIL)
<2 nsALL INPUT PULSES90%10%
90%10%<2 ns170Ω(COM’L)236Ω(MIL)
(a)
Equivalent to:
(b)
(c)
THÉVENIN EQUIVALENT
99Ω(COM’L)
136Ω(MIL)2.08V (COM'L)
OUTPUT2.13V (MIL)
5 OR 35 pF
Document #: 38-03007 Rev. *CPage 16 of 62
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AC Characteristics
3.3V AC Test Loads and Waveforms
3.3VOUTPUT
35 pF
INCLUDINGJIG ANDSCOPE
295Ω(COM’L)393Ω(MIL)
295Ω(COM'L)393Ω(MIL)
3.3VOUTPUT
5 pF
INCLUDINGJIG ANDSCOPE
Ultra37000 CPLD Family
ALL INPUT PULSES
3.0V
90%10%90%10%<2 ns340Ω(COM’L)453Ω(MIL)
340Ω(COM'L)
GND453Ω(MIL)
<2 ns(a)
Equivalent to:
THÉVENIN EQUIVALENT
(b)
(c)
OUTPUT
158Ω(COM’L)270Ω(MIL)1.77V (COM'L)
1.77V (MIL)5 OR 35 pF
Parameter[11]tER(–)
VX1.5VOutput Waveform—Measurement LevelVOH
tER(+)
2.6V0.5V
VXVX
VOL
tEA(+)
1.5V0.5V
VX
tEA(–)
Vthe
0.5V
VOH
VX
0.5V
VOL
(d) Test WaveformsSwitching Characteristics Over the Operating Range[12]
Parameter
Combinatorial Mode ParameterstPD[13, 14, 15]tPDL[13, 14, 15]tPDLL[13, 14, 15]tEA[13, 14, 15]tER[11, 13]tWL
Input to Combinatorial Output
Input to Output Through Transparent Input or Output LatchInput to Output Through Transparent Input and Output LatchesInput to Output EnableInput to Output Disable
Clock or Latch Enable Input LOW Time[8]nsnsnsnsnsns
Description
Unit
Input Register Parameters
Notes:
11.tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.12.All AC parameters are measured with two outputs switching and 35-pF AC Test Load.13.Logic Blocks operating in Low-Power Mode, add tLP to this spec.14.Outputs using Slow Output Slew Rate, add tSLEW to this spec.15.When VCCO = 3.3V, add t3.3IO to this spec.
Document #: 38-03007 Rev. *CPage 17 of 62
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Switching Characteristics Over the Operating Range[12] (continued)
ParametertWHtIStIH
tICO[13, 14, 15]tICOL[13, 14, 15]tCO[14, 15]tS[13]tH
tCO2[13, 14, 15]tSCS[13]tSL[13]tHL
Clock or Latch Enable Input HIGH Time[8]Input Register or Latch Set-up TimeInput Register or Latch Hold Time
Input Register Clock or Latch Enable to Combinatorial Output
Description
Ultra37000 CPLD Family
Unitnsnsnsnsnsnsnsnsnsnsnsns
Input Register Clock or Latch Enable to Output Through Transparent Output LatchSynchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to OutputSet-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch EnableRegister or Latch Data Hold Time
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output Delay (Through Logic Array)
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array)
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0 CLK1, CLK2, or CLK3) or Latch Enable
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable
Product Term Clock or Latch Enable (PTCLK) to Output
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)Register or Latch Data Hold Time
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or Latch Enable (PTCLK)
Buried Register Used as an Input Register or Latch Data Hold Time
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)
Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3)
Maximum Frequency with Internal Feedback (Lesser of 1/tSCS, 1/(tS + tH), or 1/tCO)[5]Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS+tH), or 1/tCO)[5]
Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH)[5]Synchronous Clocking Parameters
Product Term Clocking ParameterstCOPT[13, 14, 15]tSPTtHPTtISPT[13]tIHPT
tCO2PT[13, 14, 15]tICS[13]nsnsnsnsnsnsns
Pipelined Mode Parameters
Operating Frequency ParametersfMAX1fMAX2fMAX3fMAX4
MHzMHzMHz
Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), MHzor 1/tSCS)[5]
Asynchronous Reset Width[5]Asynchronous Reset Recovery Time[5]Asynchronous Reset to OutputAsynchronous Preset Width[5]Asynchronous Preset Recovery Time[5]Asynchronous Preset to OutputLow Power Adder
Slow Output Slew Rate Adder3.3V I/O Mode Timing Adder[5]nsnsnsnsnsnsnsnsns
Reset/Preset ParameterstRWtRR[13]tRO[13, 14, 15]tPWtPR[13]tPO[13, 14, 15]tLPtSLEWt3.3IO
User Option Parameters
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Switching Characteristics Over the Operating Range[12] (continued)
Parameter
JTAG Timing ParameterstS JTAGtH JTAGtCO JTAGfJTAG
Set-up Time from TDI and TMS to TCK[5]Hold Time on TDI and TMS[5]Falling Edge of TCK to TDO[5]Maximum JTAG Tap Controller Frequency[5]Description
Ultra37000 CPLD Family
Unitnsnsnsns
Switching Characteristics Over the Operating Range[12]
200 MHz
Max.Min.ParametertPD[13, 14, 15]tPDL[13, 14, 15]tPDLL[13, 14, 15]tEA[13, 14, 15]tER[11, 13]tWLtWHtIStIH
tICO[13, 14, 15]tICOL[13, 14, 15]tCO [14, 15]tS[13]tH
tCO2[13, 14, 15]tSCS[13]tSL[13]tHL
tCOPT[13, 14, 15]tSPTtHPTtISPT[13]tIHPT
15]
167 MHz
Max.Min.154 MHz
Max.Min.143 MHz
Max.Min.125 MHz
Max.Min.100 MHz
Max.Min.83 MHz
Max.Min.66 MHz
Max.20222424245544
242610100
2415150
2077019
30Min.Unitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
Combinatorial Mode Parameters
61112882.52.522
1112440
9.557.50
72.52.506
12
2.52.506.5
1467.50
10
2.52.506.5
15
40
10
6.58.50
10
3307.5
19
2.52.522
11124
50
11
790
13
5509
19
6.512.513.58.58.5
2.52.522
11124.5
50
12
8[16]100
13
5.55.5011
21
7.514.515.51111
2.52.522
12.5146
5.5[16]0
14
10120
13
66014
24
8.516171313
3322
12.5166.5[16]6[17]0
16
12150
15
1016.517.51414
332.52.5
16186.5[17]8[18]0
19
1217181616
4433
19218[18]1519201919
Input Register Parameters
Synchronous Clocking Parameters
Product Term Clocking Parameters
tCO2PT[13, 14, Pipelined Mode ParameterstICS[13]5
6
6
7
8[16]10
12
15
ns
Notes:
16.The following values correspond to the CY37512 and CY37384 devices: tCO = 5 ns, tS = 6.5 ns, tSCS = 8.5 ns, tICS = 8.5 ns, fMAX1 = 118 MHz.
17.The following values correspond to the CY37192V and CY37256V devices: tCO = 6 ns, tS = 7 ns, fMAX2 = 143 MHz, fMAX3 = 77 MHz, and fMAX4 = 100 MHz;
and for the CY37512 devices: tS = 7 ns.
18.The following values correspond to the CY37512V and CY37384V devices: tCO = 6.5 ns, tS = 9.5 ns, and fMAX2 = 105 MHz.
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Switching Characteristics Over the Operating Range[12] (continued)
200 MHz
Max.Min.ParameterfMAX1fMAX2fMAX3fMAX4tRWtRR[13]tRO[13, 14, 15]tPWtPR[13]tPO[13, 14, 15]tLPtSLEWt3.3IO[19]tS JTAGtH JTAGtCO JTAGfJTAG
020
2020810
122.530.3
020
2020167 MHz
Max.Min.154 MHz
Max.Min.143 MHz
Max.Min.125 MHz
Max.Min.Ultra37000 CPLD Family
100 MHz
Max.Min.83 MHz
Max.Min.66 MHz
Max.262022212.530.3020
2020
2020
020
2020262.530.3Min.UnitMHzMHzMHzMHznsnsnsnsnsnsnsnsnsnsnsnsMHz
Operating Frequency Parameters
200200125167810
12
810
132.530.3
020
2020
167200125167810
13
810
132.530.3
020
2020
154200105154810
13
810
142.530.3
020
2020
14316791125810
14
1012
152.530.3
020
125[16]154831181012
15
1214
182.530.3
100153[17]80[17]1001214
18
151783125[18]62.5831517
21
6610050662022
Reset/Preset Parameters
User Option Parameters
JTAG Timing Parameters
Switching Waveforms
Combinatorial Output
INPUT
tPD
COMBINATORIAL
OUTPUT
Note:
19.Only applicable to the 5V devices.
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Switching Waveforms (continued)
Registered Output with Synchronous Clocking
INPUT
tS
SYNCHRONOUS
CLOCK
tCO
REGISTERED
OUTPUT
tH
Ultra37000 CPLD Family
tCO2
REGISTERED
OUTPUT
tWH
SYNCHRONOUS
CLOCK
tWL
Registered Output with Product Term ClockingInput Going Through the Array
INPUT
tSPT
PRODUCT TERM
CLOCK
tCOPT
REGISTERED
OUTPUT
tHPT
Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register
INPUT
tISPT
PRODUCT TERM
CLOCK
tCO2PTREGISTERED
OUTPUT
tIHPT
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Switching Waveforms (continued)
Latched Output
INPUT
tSL
LATCH ENABLE
tPDL
LATCHEDOUTPUT
tHL
Ultra37000 CPLD Family
tCO
Registered Input
REGISTERED
INPUT
tIS
INPUT REGISTER
CLOCK
tICO
COMBINATORIAL
OUTPUT
tIH
tWH
CLOCK
tWL
Clock to Clock
INPUT REGISTER
CLOCK
tICS
OUTPUT
REGISTER CLOCK
tSCS
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Switching Waveforms (continued)
Latched Input
LATCHED INPUT
tIS
LATCH ENABLE
tPDL
COMBINATORIAL
OUTPUT
tIH
Ultra37000 CPLD Family
tICO
tWH
LATCH ENABLE
tWL
Latched Input and Output
LATCHED INPUT
tPDLL
LATCHEDOUTPUT
tICOLINPUT LATCH
ENABLE
tICS
OUTPUT LATCH
ENABLE
tSL
tHL
tWH
LATCHENABLE
tWL
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Switching Waveforms (continued)
Asynchronous Reset
tRW
INPUT
tRO
REGISTERED
OUTPUT
Ultra37000 CPLD Family
tRR
CLOCK
Asynchronous Preset
tPW
INPUT
tPO
REGISTERED
OUTPUT
tPR
CLOCK
OutputEnable/Disable
INPUT
tER
OUTPUTS
tEA
Document #: 38-03007 Rev. *CPage 24 of 62
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Ultra37000 CPLD Family
Power Consumption
Typical 5.0V Power ConsumptionCY37032
60High Speed5040Low Power)Am( 30ccI20100050100150200250Frequency (MHz)The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCY370
CC = 5.0V, TA = Room Temperature
9080High Speed7060)A50mLow Power( ccI403020100020406080100120140160180Frequency (MHz)The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
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Typical 5.0V Power Consumption (continued)CY37128
160Ultra37000 CPLD Family
140High Speed120100Icc (mA)Low Power806040200020406080100120140160180Frequency (MHz)The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
CY37192
300250High Speed200Icc (mA)150Low Power100500020406080100120140160180Frequency (MHz)The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
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Typical 5.0V Power Consumption (continued)CY37256
300Ultra37000 CPLD Family
High Speed250200Low PowerIcc (mA)150100500020406080100120140160180Frequency (MHz)The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
CY37384
500450High Speed400350300Icc (mA)250Low Power200150100500020406080100120140160Frequency (MHz)The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
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Typical 5.0V Power Consumption (continued)CY37512
600Ultra37000 CPLD Family
High Speed500400Icc (mA)300Low Power2001000020406080100120140160Frequency (MHz)The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
Typical 3.3V Power ConsumptionCY37032V
30High Speed25Low Power20Icc (mA)151050020406080100120140160Frequency (MHz)The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Document #: 38-03007 Rev. *CPage 28 of 62
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Typical 3.3V Power Consumption (continued)CY370V
45Ultra37000 CPLD Family
High Speed403530Low PowerIcc (mA)2520151050020406080100120140Frequency (MHz)The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
CY37128V
80High Speed706050Low PowerIcc (mA)403020100020406080100120140Frequency (MHz)The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Document #: 38-03007 Rev. *CPage 29 of 62
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Typical 3.3V Power Consumption (continued)CY37192V
120Ultra37000 CPLD Family
High Speed10080Low PowerIcc (mA)6040200020406080100120Frequency (MHz)The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
CY37256V
140120High Speed100Low PowerIcc (mA)806040200020406080100120Frequency (MHz)The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Document #: 38-03007 Rev. *CPage 30 of 62
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Typical 3.3V Power Consumption (continued)CY37384V
200180Ultra37000 CPLD Family
High Speed160140Low Power120Icc (mA)1008060402000102030405060708090Frequency (MHz)The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
CY37512V
250200High Speed150Low PowerIcc (mA)1005000102030405060708090Frequency (MHz)The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
Document #: 38-03007 Rev. *CPage 31 of 62
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Pin Configurations[20]
Ultra37000 CPLD Family
44-pin TQFP (A44)
TopView
I/O0GNDVCCOI/O31I/O30I/O29I/O4I/O3I/O2I/O1I/O284443424140393837363534
I/O5/TCK
1
33I/O27/TDII/O62
32I/O26I/O7331I/O25CLK2/I0430I/O24JTAGEN529CLK1/I4GND628
GNDCLK0/I1
727I3I/O88
26CLK3/I2I/O9925I/O23I/O101024I/O22I/O11
1123I/O21
1213141516171819202122
2S45C678O0O1MCD1TO1VND/O1GOO1O1O2////I/I/T/IIII/I391OO1//II44-pin PLCC (J67) / CLCC (Y67)
TopView
O109843210D3322OOOOONCCOOOO/////////IIIIIGVIIII6543214443424140
I/O5/TCK
739I/O27/TDII/OI/O683826I/OI/O793725CLK1036I/O24JTAG2/I0EN
1135CLK1/I4GND1234GNDCLK33I3
0/I1
13I/O32CLK8143/I2I/O31I/O91523I/O1630I/O2210I/O17
29
I/O1121
18192021222324252627282S45CMD678NO0O1TO1/O1C/I/VIGO1O1D///O1III/TO2/I/I39O1O1//IINote:
20.For 3.3V versions (Ultra37000V), VCCO = VCC.
Document #: 38-03007 Rev. *C
Page 32 of 62
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Pin Configurations[20] (continued)
48-ball Fine-Pitch BGA (BA50)
Top View
1
2
3
4
5
6
7
8
Ultra37000 CPLD Family
A
I/O5 VTCK
CCI/O3I/O1I/O31I/O30VCC
I/O27 TDI
B
VCCI/O4I/O2I/O0I/O29I/O28I/O26CLK1/ I4
C
CLK2/ I0I/O7I/O6
GNDGND
I/O25I/O24I3
D
JTAGENI/O8I/O9
GNDGND
I/O22I/O23CLK3/ I2
E
CLK0/ I1I/O12I/O11I/O10I/O16I/O20I/O21VCC
F
I/OVI/OVTMS
13 CC14I/O15I/O17I/O18CC
I/O19 TDO
84-lead PLCC (J83) / CLCC (Y84)
Top View
NED76543210OD6362616059585756NOOOOOOOOCCNCAGGVCTOOOOOOOO////////////////IIIIIIIIGVJIIIIIIII1110
987654321848382818079787776
75I/O74GND81273I/OI/O559
1372I/O54/TDII/O10/TCK
1471I/OI/O53111570I/OI/O5212166917I/OI/O511368I/OI/O18501467I/OI/O19491566I/OCLK480/I02065CLK3/I4VCCO21GNDGND22CLK63VCCO1/I1
23I/O62CLK2/I31624I/O61I/O471725I/O60I/O461826I/O59I/O451927I/O58I/O442028I/O57I/O432129I/O56I/O42223055I/OI/O41233154
I/O3340
GND
32
343536373839404142434445474849505152
53
459012345679D22MS78222332OD2333333OD3NOOITOOOCN[TOG///OOCGCOOOOOO////////II/////VIIIIIIIIIIIIC26V83O/OI/INote:
21.This pin is a N/C, but Cypress recommends that you connect it to VCC to ensure future compatibility.
Document #: 38-03007 Rev. *C
Page 33 of 62
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Pin Configurations[20] (continued)
100-lead TQFP (A100)
Top View
I/O6362616059Ultra37000 CPLD Family
5857VCCO1I/O0VCCOVCCN/C56GNDGND76543NC2NC10099979695949392919088878685848382818079787776
TCKGNDI/O8I/O9I/O10I/O11I/O12I/O13I/O14I/O15CLK0/I0VCCON/CGNDCLK1/I1
I/O16I/O17I/O18I/O19I/O20I/O21I/O22I/O23VCCONC
123456710111213141516171819202122232425
262728293031323334353637383940414243444547484950
757473727170696867666563626160595857565554535251
TDIVCCOI/O55I/O54I/O53I/O52I/O51I/O50I/O49I/O48CLK3/I4GNDNCVCCOCLK2/I3I/O47I/O46I/O45I/O44I/O43I/O42I/O41I/O40GNDNC
VCC[21]I/O32TMSI/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O31I/O33I/O34I/OI/O35I/O36I/O37I/O38I/O39GNDGNDVCCODocument #: 38-03007 Rev. *C
VCCOTDONCI2NCI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OPage 34 of 62
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Ultra37000 CPLD Family
Pin Configurations[20] (continued)
100-ball Fine-Pitch BGA (BB100) for CY370V
Top View
1
23456710ANCNCI/O7I/O5I/O2I/O62I/O60I/O58I/O57I/O56BI/O9I/O8I/O6I/O4I/O1I/O63VCCI/O59I/O55NCCI/O10TCKVCCI/O3NCNCI/O61VCCTDII/O54D
I/O11
NC
I/O12
I/O13
I/O0
NC
I/O51
I/O52
CLK3I/O53
/ I4E
I/O14
CLK0I/O15
NCGNDGND
I/O48I/O49CLK2I/O50
/ I0/ I3FI/O17NCNCI/O16GNDGNDNCNCI2I/O47G
I/O22
CLK1I/O21
I/O19
I/O18
I/O46
I/O45
I/O44
NC
I/O43
/ I1HI/O23TMSVCCI/O20NCI/O32I/O42VCCTDOI/O41JNCI/O26I/O28NCI/O31I/O33I/O35I/O37I/O39I/O40K
I/O24
I/O25
I/O27
I/O29
I/O30
I/O34
I/O36
I/O38
NC
NC
100-ball Fine-Pitch BGA (BB100) for CY37128V
Top View
1
23456710ANCI/O9I/O8I/O6I/O3I/O76I/O74I/O72I/O71I/O70BI/O11I/O10I/O7I/O5I/O2I/O77VCCI/O73I/O68I/O69C
I/O12I/O13VCCI/O4I/O1I/O78I/O75VCCI/O67I/O66TCKTDID
I/O14
NC
I/O15
I/O16
I/O0
I/O79
I/O63
I/O
CLK3I/O65
/ I4E
I/O17
CLK0I/O18I/O19
GNDGND
I/O60I/O61CLK2I/O62
/ I0
/ I3FI/O22JTAGI/O21I/O20GNDGNDI/O59I/O58II/OEN
257G
I/O27
CLK1I/O26
I/O24
I/O23
I/O56
I/O55
I/O54
NC
I/O53
/ I1H
I/O28I/O33VCCI/O25I/O39I/O40I/O52VCCI/O47I/O51TMSTDOJI/O29I/O32I/O35VCCI/O38I/O41I/O43I/O45I/O48I/O50K
I/O30
I/O31
I/O34
I/O36
I/O37
I/O42
I/O44
I/O46
I/O49
NC
Document #: 38-03007 Rev. *CPage 35 of 62
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Pin Configurations[20] (continued)
160-Lead TQFP (A160) / CQFP (U162) for CY37128(V) and CY37256(V)
Top View
Ultra37000 CPLD Family
GNDI/O16I/O17I/O18I/O19I/O20/TCK
I/O21I/O22I/O23GNDI/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O31CLK0/I0VCCOGNDCLK1/I1I/O32I/O33I/O34I/O35I/O36I/O37I/O38I/O39GNDI/O40I/O41I/O42I/O43I/O44I/O45I/O46I/O47VCCO
123456710111213141516171819202122232425262728293031323334353637383940
4142434445474849505152535455565758596061626365666768697071727374757677787980160159158157156155154153152151150149148147146145144143142141140139138137136135134133132131130129128127126125124123122121VCCOI/O15I/O14I/O13I/O12I/O11I/O10I/O9I/O8GNDI/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0VCCOGNDVCCJTAGENI/O127I/O126I/O125I/O124I/O123I/O122I/O121I/O120GNDI/O119I/O118I/O117I/O116I/O115I/O114I/O113I/O112GND1201191181171161151141131121111101091081071061051041031021011009997969594939291908887868584838281
VCCOI/O111I/O110I/O109
I/O108/TDII/O107I/O106I/O105I/O104GNDI/O103I/O102I/O101I/O100I/O99I/O98I/O97I/O96CLK3/I4GNDVCCOCLK2/I3I/O95I/O94I/O93I/O92I/O91I/O90I/OI/O88GNDI/O87I/O86I/O85I/O84I/O83I/O82I/O81I/O80GND
Document #: 38-03007 Rev. *C
GNDI/O48I/O49I/O50I/O51I/O52/TMSI/O53I/O54I/O55GNDI/O56I/O57I/O58I/O59I/O60I/O61I/O62I/O63I2VCCOGNDVCCI/OI/O65I/O66I/O67I/O68I/O69I/O70I/O71GNDI/O72I/O73I/O74I/O75I/O76/TDOI/O77I/O78I/O79VCCOPage 36 of 62
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Pin Configurations[20] (continued)
160-Lead TQFP (A160) for CY37192(V)
Top View
Ultra37000 CPLD Family
GNDNCI/O16I/O17I/O18TCKI/O19I/O20I/O21GNDI/O22I/O23I/O24I/O25I/O26I/O27I/O28I/O29CLK0/I0VCCOGNDCLK1/I1I/O30I/O31I/O32I/O33I/O34I/O35I/O36I/O37GNDI/O38I/O39I/O40I/O41I/O42I/O43I/O44I/O45VCCO
123456710111213141516171819202122232425262728293031323334353637383940
4142434445474849505152535455565758596061626365666768697071727374757677787980160159158157156155154153152151150149148147146145144143142141140139138137136135134133132131130129128127126125124123122121VCCOI/O15I/O14I/O13I/O12I/O11I/O10I/O9I/O8GNDI/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0VCCOGNDVCCNCI/O119I/O118I/O117I/O116I/O115I/O114I/O113I/O112GNDI/O111I/O110I/O109I/O108I/O107I/O106I/O105NCGND1201191181171161151141131121111101091081071061051041031021011009997969594939291908887868584838281
VCCOI/O104I/O103I/O102TDII/O101I/O100I/O99I/O98GNDI/O97I/O96I/O95I/O94I/O93I/O92I/O91I/O90CLK3/I4GNDVCCOCLK2/I3I/OI/O88I/O87I/O86I/O85I/O84I/O83I/O82GNDI/O81I/O80I/O79I/O78I/O77I/O76I/O75NCGND
GNDNCI/O46I/O47I/O48TMSI/O49I/O50I/O51GNDI/O52I/O53I/O54I/O55I/O56I/O57I/O58I/O59I2VCCOGNDVCCI/O60I/O61I/O62I/O63I/OI/O65I/O66I/O67GNDI/O68I/O69I/O70I/O71Document #: 38-03007 Rev. *C
TDOI/O72I/O73I/O74VCCOPage 37 of 62
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Pin Configurations[20] (continued)
208-Lead PQFP (N208) / CQFP (U208)
Top View
Ultra37000 CPLD Family
20820720620520420320220120019919819719619519419319219119011881871861851841831821811801791781771761751741731721711701691681671661651163162161160159158157VCCVCC0I/O19I/O18I/O17I/O16I/O15NCI/O14I/O13I/O12I/O11I/O10GNDI/O9I/O8I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0VCC0GNDVCCNCI/O159I/O158I/O157I/O156I/O155NCI/O154I/O153I/O152I/O151I/O150GNDI/O149I/O148I/O147I/O146I/O145I/O144I/O143I/O142I/O141I/O140NCGND156155154153152151150149148147146145144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109108107106105
Document #: 38-03007 Rev. *C
GNDI/O60I/O61I/O62I/O63I/OTMSI/O65I/O66I/O67I/O68I/O69GNDI/O70I/O71I/O72I/O73I/O74NCI/O75I/O76I/O77I/O78I/O79I2VCC0GNDVCCI/O80I/O81I/O82I/O83I/O84I/O85I/O86I/O87I/O88I/OGNDI/O90I/O91I/O92I/O93I/O94GNDTDOI/O95I/O96I/O97I/O98I/O99VCC053545556575859606162636566676869707172737475767778798081828384858687809192939495969799100101102103104GNDI/O20I/O21I/O22I/O23I/O24TCKI/O25I/O26I/O27I/O28I/O29GNDI/O30I/O31I/O32I/O33I/O34NCI/O35I/O36I/O37I/O38I/O39CLK0/I0VCCOGNDNCCLK1/I1I/O40I/O41I/O42I/O43I/O44I/O45I/O46I/O47I/O48I/O49GNDI/O50I/O51I/O52I/O53I/O54NCI/O55I/O56I/O57I/O58I/O59VCC01234567101112131415161718192021222324252627282930313233343536373839404142434445474849505152
VCCOI/O139I/O138I/O137I/O136I/O135TDII/O134I/O133I/O132I/O131I/O130GNDI/O129I/O128I/O127I/O126I/O125I/O124I/O123I/O122I/O121I/O120CLK3/I4VCCGNDVCCOGNDCLK2/I3I/O119I/O118I/O117I/O116I/O115NCI/O114I/O113I/O112I/O111I/O110GNDI/O109I/O108I/O107I/O106I/O105I/O104I/O103I/O102I/O101I/O100GND
Page 38 of 62
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Pin Configurations[20] (continued)
256-Ball PBGA (BG256)
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Ultra37000 CPLD Family
151617181920
AGND
I/O21
NC
I/O16I/O12I/O9I/O7I/O4I/O0I/O190I/O1I/O186I/O182
NC
I/O178I/O175
NCNC
I/O169I/O168
A
B
I/O23I/O20I/O19I/O18I/O15I/O11I/O8I/O5I/O1I/O191I/O187I/O185I/O181
NCNC
I/O174I/O171I/O170
NC
I/O166
B
CNCNC
I/O22
NC
I/O17I/O14I/O10I/O6I/O2
NC
I/O188I/O184I/O180I/O179I/O176I/O173I/O172I/O167I/O165I/O162
C
D
I/O24
NCNCGNDNC
VCCOI/O13
GND
I/O3
NC
VCCI/O183
GND
I/O177VCCO
NCGND
I/O1
TDI
I/O160
D
E
I/O27I/O26I/O25
NC
I/O163I/O161I/O159I/O156
E
F
I/O30
TCK
I/O28VCCOVCCOI/O158
NC
I/O154
F
G
I/O33I/O32I/O31I/O29I/O157I/O155I/O153I/O152
G
H
I/O35
NC
I/O34
GNDGNDGNDGNDGNDGNDGNDGND
I/O151I/O150I/O149
H
J
I/O39I/O38I/O37I/O36
GNDGNDGNDGNDGNDGND
I/O148I/O147I/O146I/O145
J
K
I/O42I/O40I/O41VCC
GNDGNDGNDGNDGNDGND
I/O144CLK3/I4
NCNCK
L
I/O43I/O44I/O45I/O46
GNDGNDGNDGNDGNDGND
VCCCLK2/I3I/O143
NCL
M
I/O47CLK0/I0CLK1/I1I/O48
GNDGNDGNDGNDGNDGND
I/O139I/O140I/O141I/O142
M
N
I/O49I/O50I/O51
GNDGNDGNDGNDGNDGNDGNDGND
I/O136I/O137I/O138
N
P
I/O52I/O53I/O55I/O58I/O131I/O133I/O134I/O135
P
R
I/O54I/O56I/O59VCCOVCCOI/O130
NC
I/O132
R
T
I/O57I/O60I/O62I/O65I/O124I/O127I/O128I/O129
T
U
I/O61I/O63I/O66
GND
I/O76VCCOI/O82
GND
I/O91VCCI/O98I/O102
GND
I/O112VCCO
NCGND
I/O123I/O122I/O126
U
V
I/OI/O67I/O69I/O75I/O78I/O81I/O85I/O88I/O92I2I/O97I/O101I/O105I/O109I/O113
TDO
I/O114I/O117I/O121I/O125
V
W
I/O68I/O70I/O72I/O74I/O79I/O83I/O86I/OI/O93I/O95I/O96I/O100I/O104I/O107I/O110
NCNC
I/O115I/O118I/O120
W
Y
I/O71I/O73I/O77
TMS
I/O80I/O84I/O87I/O90I/O94
NCNC
I/O99I/O103I/O106I/O108I/O111
NCNC
I/O116I/O119
Y
12345671011121314151617181920
Document #: 38-03007 Rev. *CPage 39 of 62
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Pin Configurations[20] (continued)
256-Ball Fine-Pitch BGA (BB256)
Top View
Ultra37000 CPLD Family
1
23456710111213141516A
GND
GND
I/O26
I/O24
I/O20
VCC
I/O11
GND
GND
I/O18
VCC
I/O17
I/O17
I/O16
GND
GND
6
7
2
7
BGND
I/O27I/O25I/O23I/O19I/O15I/O10
GNDGND
I/O18
I/O18
I/O17
I/O17
I/O16
I/O16
GND
5
1
6
1
6
5
C
I/O29I/O28
NC
I/O22I/O18I/O14I/O9I/O4I/O19
I/O18
I/O18
I/O17
I/O17
NC
I/O16
I/O16
1
4
0
5
0
3
4
D
I/O32I/O31I/O30
NC
I/O17I/O13I/O8I/O3I/O19
I/O18
I/O17
I/O17
I/O16
I/O16
I/O16
I/O16
0
3
9
4
9
0
1
2
E
I/O35I/O34I/O33I/O21I/O16I/O12I/O7I/O2I/O18
VCCI/O17
I/O17
I/O16
I/O15
I/O15
I/O15
9
8
3
8
7
8
9
F
VCCI/O38I/O37I/O36
TCK
VCCI/O6I/O1I/O18
I/O18
VCC
TDI
I/O15
I/O15
I/O15
VCC
8
2
4
5
6
G
I/O43I/O42I/O41I/O40VCCI/O39I/O5I/O0I/O18
I/O14
I/O14
CLK3 I/O15
I/O15
I/O15
I/O15
7
8
9
/I40
1
2
3
HGNDGND
I/O47I/O46
CLK0 I/O45I/O44
GNDGND
I/O14
I/O14
CLK2 I/O14
I/O14
GNDGND
/I04
5
/I36
7
JGNDGND
I/O51I/O50NC
I/O49I/O48
GNDGND
I/O14
I/O14
I2
I/O14
I/O14
GNDGND
0
1
2
3
K
I/O57I/O56I/O55I/O54
CLK1 I/O53I/O52I/O91I/O96I/O10
I/O13
VCCI/O13
I/O13
I/O13
I/O13
/I11
5
6
7
8
9
L
VCCI/O60I/O59I/O58TMS
VCCI/O86I/O92I/O97I/O10
VCC
TDO
I/O13
I/O13
I/O13
VCC
2
2
3
4
M
I/O63I/O62I/O61I/O72I/O77I/O82VCCI/O93I/O98I/O10
I/O10
I/O11
I/O11
I/O12
I/O13
I/O13
3
8
2
7
9
0
1
N
I/O66I/O65I/OI/O73I/O78I/O83I/O87I/O94I/O99I/O10
I/O10
I/O11
NC
I/O12
I/O12
I/O12
4
9
3
6
7
8
P
I/O68I/O67
NC
I/O74
I/O79
I/O84I/O88I/O95I/O10
I/O10
I/O11
I/O11
I/O11
NC
I/O12
I/O12
0
5
0
4
8
4
5
RGND
I/O69I/O70I/O75I/O80I/O85I/O
GNDGND
I/O10
I/O11
I/O11
I/O11
I/O12
I/O12
GND
6
1
5
9
1
3
TGNDGND
I/O71I/O76I/O81VCCI/O90
GNDGND
I/O10
VCCI/O11
I/O12
I/O12
GNDGND
7
6
0
2
Document #: 38-03007 Rev. *CPage 40 of 62
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Pin Configurations[20] (continued)
352-Lead BGA (BG352)
Top View
1ABCDEFGHJKLMNPRTUVWYAAABAC
2
3
4
5
6
7
8
9
10
11I/O7I/O8I/O6
12I/O4I/O5I/O3
13
14
15
16
17
Ultra37000 CPLD Family
181920212223242526
GNDGNDI/O19I/O15I/O13I/O34I/O31I/O28I/O25I/O10GND
NC
I/O18I/O17I/O14I/O35I/O32I/O29I/O26I/O11
I/O9NC
I/O1I/O263I/O260I/O257I/O254I/O239I/O237I/O232I/O229I/O250I/O248I/O244GNDGNDI/O2
VCCI/O261I/O258I/O255I/O252I/O234I/O231I/O228I/O249I/O246I/O245I/O240GND
I/O23I/O38I/O37I/O16I/O12I/O33I/O30I/O27I/O24I/O39I/O40I/O36I/O42
TCK
I/O41
NCNC
NC
I/O21I/O20VCCOVCCO
I/O0I/O262I/O259I/O256I/O253I/O238I/O235I/O233I/O230I/O251I/O247I/O225I/O224I/O227
NC
VCCOVCCOI/O236I/O243
NC
NCNC
I/O226I/O222I/O223TDI
I/O221I/O220
GNDGNDVCCOVCCOGNDGND
I/O45I/O44I/O43I/O22I/O48I/O47I/O46I/O63I/O49I/O50I/O51VCCOI/O52I/O53I/O54VCCOI/O55I/O56I/O57I0
NC
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
I/O242I/O219I/O218I/O217I/O241I/O216I/O215I/O214VCCOI/O211I/O212I/O213VCCOI/O208I/O209I/O210NC
I/O205I/O206I/O207
I4
I/O197
I/O59I/O58GND
I1
GND
GNDI/O204GND
I3
I/O61I/O60I/O
VCC
I/O203I/O202
I/O62VCCOVCCOI/O201I/O200I/O199VCCOI/O196VCCI/O198GNDI/O193I/O194I/O195GNDI/O178I/O179I/O192NC
I/O177I/O176I/O175
I/O65I/O66I/O67VCCOI/O68I/O69I/O70GNDI/O71I/O84I/O85GNDI/O88I/O87I/O86
NC
I/O91I/O90I/OVCCOI/O94I/O93I/O92VCCOI/O95I/O72I/O73I/O110I/O74I/O75I/O76I/O111I/O77I/O78I/O79
N/C
NC
I/O112I/O113VCCOVCCO
NC
GNDGNDVCCOVCCOGNDGND
I2
NC
VCCOVCCOI/O150I/O151
NC
VCCOI/O174I/O173I/O172VCCOI/O171I/O170I/O169I/O153I/O190I/O191I/O168I/O152I/O187I/O188I/O1NCNC
I/O184I/O185I/O186I/O155I/O183I/O182
I/O81I/O80I/O108N/C
ADI/O109I/O82I/O83I/O117I/O97I/O100I/O102I/O105I/O120I/O123I/O126I/O129AEAF
GND
NC
I/O133I/O136I/O139I/O142I/O157I/O159I/O161I/O163I/O166I/O146I/O180I/O181I/O154
NC
GND
I/O115I/O116I/O119I/O98I/O101I/O103I/O106I/O121I/O124I/O127VCCI/O130I/O134I/O137I/O140I/O143I/O160I/O162I/O165I/O144I/O147I/O148
GNDGNDI/O114I/O118I/O96I/O99TMSI/O104I/O107I/O122I/O125I/O128I/O131I/O132I/O135I/O138I/O141I/O156I/O158TDOI/O1I/O167I/O145I/O149GNDGND
Document #: 38-03007 Rev. *CPage 41 of 62
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Pin Configurations[20] (continued)
400-Ball Fine-Pitch BGA (BB400)
Top View
A
GND
GND
NC
I/O17NC
I/O16I/O15I/O20I/O19NC
I/O14I/O13I/O12I/O18I/O35NC
I/O29I/O28I/O27I/O26I/O34I/O33I/O37TCK
VCCVCCVCCI/O25I/O24I/O32I/O31VCCI/O62I/O63I/O67I/O71VCCI/O11
4
Ultra37000 CPLD Family
I/O11I/O10I/O9I/O8I/O7I/O6I/O5I/O30I/O60I/O61I/O66I/O70I/O12
8
GNDGND
I/O25
7
VCCVCCVCCI/O23
5
I/O23
9
I/O23
3
I/O23
2
I/O23
0
NCGNDGND
BGNDGNDGNDGNDGND
I/O25
6
I/O23
8
I/O23
1
I/O22
9
NCGNDGNDGND
CNCGNDGNDGNDGNDGND
I/O25
5
I/O23
7
I/O22
8
I/O24
5
GNDGNDGNDNC
D
I/O44I/O46I/O47I/O53VCCI/O59GND
NCGND
I/O21I/O22I/O41I/O50I/O49I/O56GND
GNDGND
I/O25
4
I/O23
6
I/O25
1
I/O24
4
I/O24
3
GNDNC
I/O22
7
E
I/O43I/O45I/O52VCCI/O58GND
I/O23I/O42I/O51VCCI/O57GND
I/O4I/O3I/O2I/O1I/O0GND
I/O26
3
I/O25
3
I/O23
4
I/O25
0
I/O24
8
NC
I/O24
1
I/O24
2
I/O22
5
I/O22
6
F
I/O40I/O39I/O48I/O55I/O65I/O69I/O85I/O90I/O75I/O77NC
I/O26
2
I/O25
2
I/O24
9
I/O24
7
I/O22
0
I/O22
1
I/O24
0
I/O22
2
I/O22
3
I/O22
4
G
I/O38I/O36I/O54I/OI/O68I/O84I/O72I/O74I/O76I/O11
6
I/O26
1
VCCI/O26
0
I/O24
6
I/O21
7
I/O21
8
I/O21
9
I/O21
2
I/O21
3
I/O21
4
I/O21
5
H
I/O25
9
VCCI/O20
3
TDI
I/O21
6
I/O21
0
I/O21
1
VCCI/O20
7
VCCI/O20
8
VCCI/O20
9
J
VCCCLK0 /I0NC
I/O25
8
I/O20
2
CLK3 /I4CLK2 /I3I2VCCTDO
I/O20
4
I/O20
5
I/O20
6
KGND
I/O19
8
I/O19
9
I/O20
0
I/O20
1
GNDGNDGNDGND
LGNDGNDGNDGNDGNDGND
I/O19
3
I/O19
5
I/O19
6
I/O19
7
GNDGNDGNDGND
M
I/OVCCI/O95I/O80I/O82I/O83NC
I/O88VCCI/O94I/O79I/O81NC
I/O87VCCI/O93I/O78I/O11
0
I/O86I/O91I/O92I/O10
8
CLK1 /I1TMS
I/O12
6
I/O13
2
I/O19
2
I/O19
4
I/O17
4
I/O17
5
I/O17
6
I/O17
7
I/O17
8
I/O17
9
N
I/O12
7
I/O13
3
I/O16
2
VCCI/O16
3
I/O18
0
I/O16
8
I/O16
9
VCCI/O17
1
VCCI/O17
2
VCCI/O17
3
P
I/O73I/O11
5
VCCI/O12
0
I/O12
9
I/O13
4
I/O13
7
I/O18
1
I/O18
2
I/O18
3
I/O17
0
R
I/O11
7
I/O13
0
I/O13
5
I/O13
8
I/O16
4
I/O16
5
NC
I/O18
4
I/O18
5
I/O18
6
I/O18
9
I/O19
1
T
I/O10
9
I/O11
8
I/O10
2
I/O12
1
I/O13
1
I/O13
6
I/O13
9
I/O15
6
I/O16
6
I/O16
7
NC
I/O15
4
I/O15
5
I/O18
7
I/O19
0
UGND
I/O11
1
I/O11
2
I/O11
9
I/O10
4
I/O10
3
I/O12
2
GNDGND
I/O14
0
I/O15
7
I/O15
8
I/O15
0
I/O15
1
I/O15
3
GNDNC
I/O18
8
VGNDGNDGND
I/O11
3
I/O96I/O99I/O10
1
I/O10
5
VCCVCCVCC
I/O12
3
GNDGND
I/O14
1
VCCVCCVCC
I/O15
9I/O144I/O14
5
I/O15
2
GNDGNDGNDNC
WGNDGNDGNDNC
I/O97I/O10
0
I/O10
6
I/O12
4
GNDGND
I/O14
2
I/O16
0
I/O14
7
NCGNDGNDGND
YGNDGNDNC
I/O98I/O10
7
I/O12
5
GNDGND
I/O14
3
I/O16
1
I/O14
6
I/O14
8
I/O14
9
NCGNDGND
Document #: 38-03007 Rev. *CPage 42 of 62
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Ordering Information
Ultra37000 CPLD Family
C Y 3 7 5 1 2 V P 4 0 0 - 8 3 B B CCypress Semiconductor IDFamily Type37 = Ultra37000 FamilyMacrocell Density 32 = 32 Macrocells = Macrocells128 = 128 Macrocells192 = 192 MacrocellsOperating ConditionsCommercial 0°C to +70°CIndustrial-40°C to +85°CMilitary-55°C to +125°C256 = 256 Macrocells384 = 384 Macrocells512 = 512 MacrocellsPackage TypeA = Thin Quad Flat Pack (TQFP)U = Ceramic Quad Flat Pack (CQFP)N = Plastic Quad Flat Pack (PQFP)NT = Thermally Enhanced Plastic Quad Flat Pack (EQFP)J = Plastic Leaded Chip Carrier (PLCC)Y = Ceramic Leaded Chip Carrier (CLCC)BG = Ball Grid Array (BGA)BA = Fine-Pitch Ball Grid Array (FBGA) 0.8mm Lead PitchBB = Fine-Pitch Ball Grid Array (FBGA) 1.0mm Lead PitchSpeed200 = 200 MHz167 = 167 MHz154 = 154 MHz143 = 143 MHz125 = 125 MHz100 = 100 MHz 83 = 83 MHz66 = 66 MHz Operating Reference VoltageV = 3.3V Supply Voltage(5.0V if not specified)Pin CountP44 = 44 LeadsP48 = 48 LeadsP84 = 84 LeadsP100 = 100 LeadsP160 = 160 LeadsP208 = 208 LeadsP256 = 256 LeadsP352 = 352 LeadsP400 = 400 Leads5.0V Ordering InformationMacro-cells 32
Speed(MHz)200154
Ordering CodeCY37032P44-200ACCY37032P44-200JCCY37032P44-154ACCY37032P44-154JCCY37032P44-154AICY37032P44-154JI
125
CY37032P44-125ACCY37032P44-125JCCY37032P44-125AICY37032P44-125JI
200
CY370P44-200ACCY370P44-200JCCY370P84-200JCCY370P100-200AC
PackageNameA44J67A44J67A44J67A44J67A44J67A44J67J83A100
Package Type
44-Lead Thin Quad Flat Pack44-Lead Plastic Leaded Chip Carrier44-Lead Thin Quad Flat Pack44-Lead Plastic Leaded Chip Carrier44-Lead Thin Quad Flat Pack44-Lead Plastic Leaded Chip Carrier44-Lead Thin Quad Flat Pack44-Lead Plastic Leaded Chip Carrier44-Lead Thin Quad Flat Pack44-Lead Plastic Leaded Chip Carrier44-Lead Thin Quad Flat Pack44-Lead Plastic Leaded Chip Carrier84-Lead Plastic Leaded Chip Carrier100-Lead Thin Quad Flat Pack
CommercialIndustrialCommercialIndustrialCommercialOperatingRangeCommercial
Document #: 38-03007 Rev. *CPage 43 of 62
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5.0V Ordering Information (continued)
Macro-cells
Speed(MHz)154
Ordering CodeCY370P44-154ACCY370P44-154JCCY370P84-154JCCY370P100-154ACCY370P44-154AICY370P44-154JICY370P84-154JICY370P100-154AI5962-9951902QYA
125
CY370P44-125ACCY370P44-125JCCY370P84-125JCCY370P100-125ACCY370P44-125AICY370P44-125JICY370P84-125JICY370P100-125AI5962-9951901QYA
128
167
CY37128P84-167JCCY37128P100-167ACCY37128P160-167AC
125
CY37128P84-125JCCY37128P100-125ACCY37128P160-125ACCY37128P84-125JICY37128P100-125AICY37128P160-125AI5962-9952102QYA
100
CY37128P84-100JCCY37128P100-100ACCY37128P160-100ACCY37128P84-100JICY37128P100-100AICY37128P160-100AI5962-9952101QYA
192
15412583
CY37192P160-154ACCY37192P160-125ACCY37192P160-125AICY37192P160-83ACCY37192P160-83AI
PackageNameA44J67J83A100A44J67J83A100Y67A44J67J83A100A44J67J83A100Y67J83A100A160J83A100A160J83A100A160Y84J83A100A160J83A100A160Y84A160A160A160A160A160
Ultra37000 CPLD Family
OperatingRangeCommercial
Package Type
44-Lead Thin Quad Flat Pack44-Lead Plastic Leaded Chip Carrier84-Lead Plastic Leaded Chip Carrier100-Lead Thin Quad Flat Pack44-Lead Thin Quad Flat Pack44-Lead Plastic Leaded Chip Carrier84-Lead Plastic Leaded Chip Carrier100-Lead Thin Quad Flat Pack44-Lead Ceramic Leadless Chip Carrier44-Lead Thin Quad Flat Pack44-Lead Plastic Leaded Chip Carrier84-Lead Plastic Leaded Chip Carrier100-Lead Thin Quad Flat Pack44-Lead Thin Quad Flat Pack44-Lead Plastic Leaded Chip Carrier84-Lead Plastic Leaded Chip Carrier100-Lead Thin Quad Flat Pack44-Lead Ceramic Leadless Chip Carrier84-Lead Plastic Leaded Chip Carrier100-Lead Thin Quad Flat Pack160-Lead Thin Quad Flat Pack84-Lead Plastic Leaded Chip Carrier100-Lead Thin Quad Flat Pack160-Lead Thin Quad Flat Pack84-Lead Plastic Leaded Chip Carrier100-Lead Thin Quad Flat Pack160-Lead Thin Quad Flat Pack84-Lead Ceramic Leaded Chip Carrier84-Lead Plastic Leaded Chip Carrier100-Lead Thin Quad Flat Pack160-Lead Thin Quad Flat Pack84-Lead Plastic Leaded Chip Carrier100-Lead Thin Quad Flat Pack160-Lead Thin Quad Flat Pack84-Lead Ceramic Leaded Chip Carrier160-Lead Thin Quad Flat Pack160-Lead Thin Quad Flat Pack160-Lead Thin Quad Flat Pack160-Lead Thin Quad Flat Pack160-Lead Thin Quad Flat Pack
Industrial
MilitaryCommercial
Industrial
MilitaryCommercial
Commercial
Industrial
MilitaryCommercial
Industrial
MilitaryCommercialCommercialIndustrialCommercialIndustrial
Document #: 38-03007 Rev. *CPage 44 of 62
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5.0V Ordering Information (continued)
Macro-cells 256
Speed(MHz)154
Ordering CodeCY37256P160-154ACCY37256P208-154NCCY37256P256-154BGC
125
CY37256P160-125ACCY37256P208-125NCCY37256P256-125BGCCY37256P160-125AICY37256P208-125NICY37256P256-125BGI5962-9952302QZC
83
CY37256P160-83ACCY37256P208-83NCCY37256P256-83BGCCY37256P160-83AICY37256P208-83NICY37256P256-83BGI5962-9952301QZC
384
12583
CY37384P208-125NCCY37384P256-125BGCCY37384P208-83NCCY37384P256-83BGCCY37384P208-83NICY37384P256-83BGI
512
125
CY37512P208-125NCCY37512P256-125BGCCY37512P352-125BGC
100
CY37512P208-100NCCY37512P256-100BGCCY37512P352-100BGCCY37512P208-100NICY37512P256-100BGICY37512P352-100BGI5962-9952502QZC
83
CY37512P208-83NCCY37512P256-83BGCCY37512P352-83BGCCY37512P208-83NICY37512P256-83BGICY37512P352-83BGI5962-9952501QZC
PackageNameA160N208BG256A160N208BG256A160N208BG256U162A160N208BG256A160N208BG256U162N208BG256N208BG256N208BG256N208BG256BG352N208BG256BG352N208BG256BG352U208N208BG256BG352N208BG256BG352U208
Ultra37000 CPLD Family
OperatingRangeCommercial
Package Type
160-Lead Thin Quad Flat Pack208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array160-Lead Thin Quad Flat Pack208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array160-Lead Thin Quad Flat Pack208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array
160-Lead Ceramic Quad Flat Pack160-Lead Thin Quad Flat Pack208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array160-Lead Thin Quad Flat Pack208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array
160-Lead Ceramic Quad Flat Pack208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array352-Lead Ball Grid Array208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array352-Lead Ball Grid Array208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array352-Lead Ball Grid Array
208-Lead Ceramic Quad Flat Pack208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array352-Lead Ball Grid Array208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array352-Lead Ball Grid Array
208-Lead Ceramic Quad Flat Pack
Commercial
Industrial
MilitaryCommercial
Industrial
MilitaryCommercialCommercialIndustrialCommercial
Commercial
Industrial
MilitaryCommercial
Industrial
Military
Document #: 38-03007 Rev. *CPage 45 of 62
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3.3V Ordering Information
Macro-cells32
Speed(MHz)143100
Ordering CodeCY37032VP44-143ACCY37032VP48-143BACCY37032VP44-100ACCY37032VP48-100BACCY37032VP44-100AICY37032VP48-100BAI
143
CY370VP44-143ACCY370VP48-143BACCY370VP100-143ACCY370VP100-143BBC
100
CY370VP44-100ACCY370VP48-100BACCY370VP100-100ACCY370VP100-100BBCCY370VP44-100AICY370VP48-100BAICY370VP100-100BBICY370VP100-100AI5962-9952001QYA
128
125
CY37128VP100-125ACCY37128VP100-125BBCCY37128VP160-125AC
83
CY37128VP100-83ACCY37128VP100-83BBCCY37128VP160-83ACCY37128VP100-83AICY37128VP100-83BBICY37128VP160-83AI5962-9952201QYA
192
10066
CY37192VP160-100ACCY37192VP160-66ACCY37192VP160-66AI
Package NameA44BA50A44BA50A44BA50A44BA50A100BB100A44BA50A100BB100A44BA50BB100A100Y67A100BB100A160A100BB100A160A100BB100A160Y84A160A160A160
Ultra37000 CPLD Family
Package Type
44-Lead Thin Quad Flat Pack48-Lead Fine Pitch Ball Grid Array44-Lead Thin Quad Flat Pack48-Lead Fine Pitch Ball Grid Array44-Lead Thin Quad Flat Pack48-Lead Fine Pitch Ball Grid Array44-Lead Thin Quad Flatpack48-Lead Fine-Pitch Ball Grid Array100-Lead Thin Quad Flatpack100-Lead Fine-Pitch Ball Grid Array44-Lead Thin Quad Flatpack48-Lead Fine-Pitch Ball Grid Array100-Lead Thin Quad Flatpack100-Lead Fine-Pitch Ball Grid Array44-Lead Thin Quad Flatpack48-Lead Fine-Pitch Ball Grid Array100-Lead Fine-Pitch Ball Grid Array100-Lead Thin Quad Flatpack44-Lead Ceramic Leaded Chip Carrier100-Lead Thin Quad Flat Pack100-Lead Fine-Pitch Ball Grid Array160-Lead Thin Quad Flat Pack100-Lead Thin Quad Flat Pack100-Lead Fine-Pitch Ball Grid Array160-Lead Thin Quad Flat Pack100-Lead Thin Quad Flat Pack100-Lead Fine-Pitch Ball Grid Array160-Lead Thin Quad Flat Pack84-Lead Ceramic Leaded Chip Carrier160-Lead Thin Quad Flat Pack160-Lead Thin Quad Flat Pack160-Lead Thin Quad Flat Pack
OperatingRangeCommercialCommercialIndustrialCommercial
Commercial
Industrial
MilitaryCommercial
Commercial
Industrial
MilitaryCommercialCommercialIndustrial
Document #: 38-03007 Rev. *CPage 46 of 62
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3.3V Ordering Information (continued)
Macro-cells256
Speed(MHz)100
Ordering CodeCY37256VP160-100ACCY37256VP208-100NCCY37256VP256-100BGCCY37256VP256-100BBC
66
CY37256VP160-66ACCY37256VP208-66NCCY37256VP256-66BGCCY37256VP256-66BBCCY37256VP160-66AICY37256VP256-66BGICY37256VP256-66BBI5962-9952401QZC
384
8366
CY37384VP208-83NCCY37384VP256-83BGCCY37384VP208-66NCCY37384VP256-66BGCCY37384VP208-66NICY37384VP256-66BGI
512
83
CY37512VP208-83NCCY37512VP256-83BGCCY37512VP352-83BGCCY37512VP400-83BBC
66
CY37512VP208-66NCCY37512VP256-66BGCCY37512VP352-66BGCCY37512VP400-66BBCCY37512VP208-66NICY37512VP256-66BGICY37512VP352-66BGICY37512VP400-66BBI5962-9952601QZC
Package NameA160N208BG256BB256A160N208BG256BB256A160BG256BB256U162N208BG256N208BG256N208BG256N208BG256BG352BB400N208BG256BG352BB400N208BG256BG352BB400U208
Ultra37000 CPLD Family
OperatingRangeCommercial
Package Type
160-Lead Thin Quad Flat Pack208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array
256-Lead Fine-Pitch Ball Grid Array160-Lead Thin Quad Flat Pack208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array
256-Lead Fine-Pitch Ball Grid Array160-Lead Thin Quad Flat Pack256-Lead Ball Grid Array
256-Lead Fine-Pitch Ball Grid Array160-Lead Ceramic Quad Flat Pack208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array352-Lead Ball Grid Array
400-Lead Fine-Pitch Ball Grid Array208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array352-Lead Ball Grid Array
400-Lead Fine-Pitch Ball Grid Array208-Lead Plastic Quad Flat Pack256-Lead Ball Grid Array352-Lead Ball Grid Array
400-Lead Fine-Pitch Ball Grid Array208-Lead Ceramic Quad Flat Pack
Commercial
Industrial
MilitaryCommercialCommercialIndustrialCommercial
Commercial
Industrial
Military
Document #: 38-03007 Rev. *CPage 47 of 62
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Package Diagrams
44-leadThinPlasticQuadFlatPackA44
Ultra37000 CPLD Family
51-850-*B
44-LeadPlasticLeadedChipCarrierJ67
51-85003-*A
Document #: 38-03007 Rev. *CPage 48 of 62
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Package Diagrams (continued)
44-PinCeramicLeadedChipCarrierY67Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C51-80014-**Page 49 of 62
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Package Diagrams (continued)
Ultra37000 CPLD Family
48-Ball (7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch) Thin BGA BA48D51-85109-*C84-LeadPlasticLeadedChipCarrierJ83
51-85006-*A
Document #: 38-03007 Rev. *CPage 50 of 62
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Package Diagrams (continued)
84-PinCeramicLeadedChipCarrierY84
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C51-80095-*A
Page 51 of 62
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Package Diagrams (continued)
Ultra37000 CPLD Family
100-Pin Thin Plastic Quad Flat Pack (TQFP) A10051-85048-*BDocument #: 38-03007 Rev. *CPage 52 of 62
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Package Diagrams (continued)
Ultra37000 CPLD Family
100-Ball Thin Ball Grid Array (11 x 11 x 1.4 mm) BB100Document #: 38-03007 Rev. *C51-85107-*BPage 53 of 62
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Package Diagrams (continued)
Ultra37000 CPLD Family
160-Pin Thin Plastic Quad Flat Pack (24 x 24 x 1.4 mm) (TQFP) A160
51-85049-*BDocument #: 38-03007 Rev. *CPage 54 of 62
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Ultra37000 CPLD Family
Package Diagrams (continued)
160-Lead Ceramic Quad Flatpack (Cavity Up) U16251-80106-**Document #: 38-03007 Rev. *CPage 55 of 62
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Package Diagrams (continued)
208-Lead Plastic Quad Flatpack N208
Ultra37000 CPLD Family
51-85069-*B
Document #: 38-03007 Rev. *CPage 56 of 62
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Ultra37000 CPLD Family
Package Diagrams (continued)
208-Lead Ceramic Quad Flatpack (Cavity Up) U208
Document #: 38-03007 Rev. *C51-80105-*A
Page 57 of 62
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Package Diagrams (continued)
256-Ball FBGA (17 x 17 mm) BB256Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C51-85108-*CPage 58 of 62
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Package Diagrams (continued)
Ultra37000 CPLD Family
388-Lead PBGA (35 x 35 x 2.33 mm) BG388Document #: 38-03007 Rev. *C51-85103-*CPage 59 of 62
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Package Diagrams (continued)
400-Ball FBGA (21 x 21 x 1.4 mm) BB400
Ultra37000 CPLD Family
51-85111-*A
Warp is a registered trademark, and In-System Reprogrammable, ISR, Warp Professional, Warp Enterprise, and Ultra37000 aretrademarks, of Cypress Semiconductor.ViewDraw and SpeedWave are trademarks of ViewLogic. Windows is a registered trade-mark of Microsoft Corporation. All product and company names mentioned in this document are the trademarks of their respectiveholders.
Document #: 38-03007 Rev. *CPage 60 of 62
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Addendum
3.3V Operating Range
Ultra37000 CPLD Family
(CY370VP100-143AC, CY370VP100-143BBC, CY370VP44-143AC, CY370VP48-143BAC)
Range
Commercial
Ambient Temperature[2]0°C to +70°C
Junction Temperature
0°C to +90°C
VCC3.3V ± 0.16V
Document #: 38-03007 Rev. *CPage 61 of 62
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the useof any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorizeits products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of CypressSemiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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Document History Page
Ultra37000 CPLD Family
Document Title: Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDsDocument Number: 38-03007REV.***A*B*C
ECN NO.106272124942126262128125
Issue Date04/18/0103/21/0305/09/0307/16/03
Orig. of ChangeSZVOORTEHHOM
Description of Change
Change from Spec number: 38-00475 to 38-03007Updated 3.3V VCC requirements for –144 speedsAdded an Addendum
Changed pinout for CY37128V BB100 packageObsoleted following 3.3V PLCC packaged devices:CY37032VP44-143JCCY37032VP44-100JCCY37032VP44-100JICY370VP44-143JCCY370VP84-143JCCY370VP44-100JCCY370VP84-100JCCY370VP44-100JICY370VP84-100JICY37128VP84-125JCCY37128VP84-83JCCY37128VP84-83JI
Document #: 38-03007 Rev. *CPage 62 of 62
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