library ieee;
use ieee.std_logic_11.all; use ieee.std_logic_unsigned.all;
entity cnt2 is
port(clk,clr,cs:in std_logic;
qq:buffer std_logic_vector(3 downto 0); co:out std_logic); end cnt2;
architecture one of cnt2 is begin
process(clk,clr,cs) begin
if(clr='1')then qq<=\"0000\";
elsif(clk'event and clk='1') then if(cs='1') then if(qq=1) then qq<=\"0000\"; else
qq<=qq+1; end if; end if; end if; end process; process(qq) begin
if(qq=1) then co<='0'; else co<='1'; end if; end process; end one;
library ieee;
use ieee.std_logic_11.all; use ieee.std_logic_unsigned.all;
entity cnt6 is
port(clk,clr,cs:in std_logic;
qq:buffer std_logic_vector(3 downto 0);
co:out std_logic); end cnt6;
architecture one of cnt6 is begin
process(clk,clr,cs) begin
if(clr='1')then qq<=\"0000\";
elsif(clk'event and clk='1') then if(cs='1') then if(qq=5) then qq<=\"0000\"; else
qq<=qq+1; end if; end if; end if; end process; process(qq) begin
if(qq=5) then co<='0'; else co<='1'; end if; end process; end one;
library ieee;
use ieee.std_logic_11.all; use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk,clr,cs:in std_logic;
qq:buffer std_logic_vector(3 downto 0); co:out std_logic); end cnt10;
architecture one of cnt10 is begin
process(clk,clr,cs) begin
if(clr='1')then
qq<=\"0000\";
elsif(clk'event and clk='1') then if(cs='1') then if(qq=9) then qq<=\"0000\"; else
qq<=qq+1; end if; end if; end if; end process; process(qq) begin
if(qq=9) then co<='0'; else co<='1'; end if; end process; end one;
library ieee;
use ieee.std_logic_11.all;
entity control is
port(clk:in std_logic;
cs,clr,le:out std_logic); end control;
architecture behav of control is
signal current_state,next_state:std_logic_vector(3 downto 0); constant st0:std_logic_vector:=\"0000\"; constant st1:std_logic_vector:=\"0001\"; constant st2:std_logic_vector:=\"0011\"; constant st3:std_logic_vector:=\"0010\"; constant st4:std_logic_vector:=\"0110\"; constant st5:std_logic_vector:=\"1110\"; constant st6:std_logic_vector:=\"1111\"; constant st7:std_logic_vector:=\"1101\"; constant st8:std_logic_vector:=\"1100\"; constant st9:std_logic_vector:=\"1000\"; begin
com1:process(current_state)
begin
case current_state is
when st0=>next_state<=st1;clr<='1';cs<='0';le<='0'; when st1=>next_state<=st2;clr<='0';cs<='1';le<='0'; when st2=>next_state<=st3;clr<='0';cs<='1';le<='0'; when st3=>next_state<=st4;clr<='0';cs<='1';le<='0'; when st4=>next_state<=st5;clr<='0';cs<='1';le<='0'; when st5=>next_state<=st6;clr<='0';cs<='1';le<='0'; when st6=>next_state<=st7;clr<='0';cs<='1';le<='0'; when st7=>next_state<=st8;clr<='0';cs<='1';le<='0'; when st8=>next_state<=st9;clr<='0';cs<='1';le<='0'; when st9=>next_state<=st0;clr<='0';cs<='0';le<='1'; when others=>next_state<=st0;clr<='0';cs<='0';le<='0'; end case;
end process com1;
reg:process(clk) begin
if(clk'event and clk='1')then current_state<=next_state; end if; end process reg; end behav;
library ieee;
use ieee.std_logic_11.all; use ieee.std_logic_unsigned.all;
entity latch4 is
port(le:in std_logic;
dd:in std_logic_vector(3 downto 0); qq:out std_logic_vector(3 downto 0)); end latch4;
architecture one of latch4 is begin
process(le,dd) begin
if(le='1')then qq<=dd; end if; end process; end one;
library ieee;
use ieee.std_logic_11.all;
entity led7s is
port(din:in std_logic_vector(3 downto 0); y:out std_logic_vector(6 downto 0)); end led7s;
architecture one of led7s is begin
process(din) begin
case din is
when \"0000\"=>Y<=\"1000000\"; when \"0001\"=>Y<=\"1111001\"; when \"0010\"=>Y<=\"0100100\"; when \"0011\"=>Y<=\"0110000\"; when \"0100\"=>Y<=\"0011001\"; when \"0101\"=>Y<=\"0010010\"; when \"0110\"=>Y<=\"0000010\"; when \"0111\"=>Y<=\"1111000\"; when \"1000\"=>Y<=\"0000000\"; when \"1001\"=>Y<=\"0010000\"; when \"1010\"=>Y<=\"0001000\"; when \"1011\"=>Y<=\"0000011\"; when \"1100\"=>Y<=\"1000110\"; when \"1101\"=>Y<=\"0100001\"; when \"1110\"=>Y<=\"0000110\"; when \"1111\"=>Y<=\"0001110\"; when others=>Y<=null; end case; end process; end;