Thermal Management Strategy
As described in this section, Xilinx relies on a multi-pronged approach with regards to the heat-dissipating potential of 7series devices.
Cavity-Up Plastic BGA Packages
BGA is a plastic package technology that utilizes area array solder balls at the bottom of the package to make electrical contact with the circuit board in the users system. The area array format of solder balls reduces package size considerably when compared to leaded products. It also results in improved electrical performance as well as having higher manufacturing yields. The substrate is made of a multi-layer BT (bismaleimide triazene) epoxy-based material. Power and GND pins are grouped together and signal pins are assigned to the perimeter for ease of routing on the board. The package is offered in a die-up format and contains a wire-bond device covered with a mold compound. As shown in the cross section of Figure5-2, the BGA package contains a wire-bond die on a single-core printed circuit board with an overmold.
Plastic MoldPlated Copper ConductorSoldermaskBT (PCB Laminate)Solder BallUG475_c5_01_042012Figure 5-2:Cavity-Up Ball Grid Array Package
The key features/advantages of cavity-up BGA packages are:•••
Low profile and small footprintEnhanced thermal performanceExcellent board-level reliability
Wire-Bond Packages
Wire-bond packages meet the demands required by miniaturization while offering
improved performance. Applications for wire-bond packages are targeted to portable and consumer products where board space is of utmost importance, miniaturization is a key requirement, and power consumption/dissipation must be low. By employing 7series FPGA wire-bond packages, system designers can dramatically reduce board area requirements. Xilinx wire-bond packages are rigid BT-based substrates (see Figure5-3).
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
1ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAG34AHAJAK123456710111213141516171819202122232425262728293017171818171818171818171515151414151515171616171616161616ABCDEFGHJKLMNPRTU1403312323233331232323312323233121313121312131314VWYAAABAC13ADAEAFAGAHAJAK0140014330343434343434234567101112131415161718192021222324252627282930Power Pins#VCCO_#VCCINTVCCAUX#VCCAUX_IO_G#VCCBRAMVCCBATT_0VCCADC_0GNDADC_0###MGTVCCAUXMGTVCCAUX_G# or MGTHVCCAUX_G#MGTAVCCMGTAVCC_G# or MGTHAVCC_G#MGTAVTTMGTAVTT_G# or MGTHAVTT_G#GNDug475_c3_28_052311Figure 3-112:
FB900, FBG900, and FBV900 Packages—XC7K325T and XC7K410T
Power and GND Placement
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
FF676, FFG676, FFV676, and RF676 Packages—XC7K160T,
XA7K160T, XC7K325T, and XC7K410T
1ABCDEFGHJKLMNPRTUVWYAAABACADAEAF12345671011121314151617181920212223242526AVVVEECBBBBBCBUDEFVVEYBGHEDsssrrsBBssJKLMNPRTssUVWsYAAABACADAEAFVVV2EGVKMSSSSJsPIOL102345671011121314151617181920212223242526User I/O PinsIO_LXXY_#sIO_XX_#Transceiver PinsEVVMGTAVCC_G#MGTAVTT_G#MGTVCCAUX_G#MGTAVTTRCALMGTRREFMGTREFCLK1/0PMGTREFCLK1/0NMGTXRXPMGTXRXNMGTXTXPMGTXTXNEVMGTHAVCC_G#MGTHAVTT_G#MGTHRXPMGTHRXNMGTHTXPMGTHTXNY012PKIOMDJLCDedicated PinsCCLK_0CFGBVS_0DONE_0DXP_0DXN_0GNDADC_0INIT_B_0M0_0M1_0M2_0PROGRAM_B_0TCK_0TDI_0TDO_0TMS_0VCCADC_0VCCBATT_0nSSSSVP_0VN_0VREFP_0VREFN_0Other PinsGNDVCCAUX_IO_G#VCCAUXVCCINTVCCO_#VCCBRAMNCMulti−Function PinsBBBBBBBBUrADV_BFCS_BFOE_BMOSIFWE_BDOUT_CSO_BCSI_BPUDC_BRDWR_BRS0−RS1AD0P/AD0N−AD15P/AD15NEMCCLKVRNVRPVREFD00−D31A00−A28DQSMRCCSRCCVGug475_c3_29_090511Figure 3-113:
FF676, FFG676, FFV676, and RF676 Packages—XC7K160T, XA7K160T, XC7K325T, and
XC7K410T Pinout Diagram
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019
Chapter 3:Device Diagrams
FF901, FFG901, and FFV901 Packages—XC7K355T
1ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAK1234567101112131415161718192021222324252627282930nnnnnnnnnnnnnnnnssBsBsnnnnnsABCDEFGHJKLMNrUBBssBPRTUBBVWYAAnnnnnnnnnnnnnnnnnnnnnnnnsABACADAEAFAGAHAJAKVVVVVEEVEnnEnnVVEYEVVEVIMKCOnnnnnEVVEGBrSSSSJVEVVEVLsnVnP210nnnnnnnnnnnEnnEnnnnnnnnnnnnnnnnsssEVVEnnDEVVEnnnnnnnnEnVnVV23456nV7nVn101112131415161718192021222324252627282930User I/O PinsIO_LXXY_#sIO_XX_#Transceiver PinsEVVMGTAVCC_G#MGTAVTT_G#MGTVCCAUX_G#MGTAVTTRCALMGTRREFMGTREFCLK1/0PMGTREFCLK1/0NMGTXRXPMGTXRXNMGTXTXPMGTXTXNEVMGTHAVCC_G#MGTHAVTT_G#MGTHRXPMGTHRXNMGTHTXPMGTHTXNY012PKIOMDJLCDedicated PinsCCLK_0CFGBVS_0DONE_0DXP_0DXN_0GNDADC_0INIT_B_0M0_0M1_0M2_0PROGRAM_B_0TCK_0TDI_0TDO_0TMS_0VCCADC_0VCCBATT_0nSSSSVP_0VN_0VREFP_0VREFN_0Other PinsGNDVCCAUX_IO_G#VCCAUXVCCINTVCCO_#VCCBRAMNCMulti−Function PinsBBBBBBBBUrADV_BFCS_BFOE_BMOSIFWE_BDOUT_CSO_BCSI_BPUDC_BRDWR_BRS0−RS1AD0P/AD0N−AD15P/AD15NEMCCLKVRNVRPVREFD00−D31A00−A28DQSMRCCSRCCVGug475_c3_37_090511Figure 3-121:FF901, FFG901, and FFV901 Packages—XC7K355T Pinout Diagram
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2019