Am29LV800B
Data Sheet
RETIRED PRODUCT
This product has been retired and is not recommended for designs. For new and current designs,S29AL008D supersedes Am29LV800B and is the factory-recommended migration path. Please referto the S29AL008D datasheet for specifications and ordering information. Availability of this docu-ment is retained for reference and historical purposes only.
July 2003
The following document specifies Spansion memory products that are now offered by both AdvancedMicro Devices and Fujitsu. Although the document is marked with the name of the company thatoriginally developed the specification, these products will be offered to customers of both AMD andFujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Anychanges that have been made are the result of normal datasheet improvement and are noted in thedocument revision summary, where supported. Future routine revisions will occur when appro-priate, and changes will be noted in a revision summary.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansionmemory solutions.
PublicationNumber21490RevisionGAmendment5IssueDateMay 25, 2005
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PRELIMINARY (DRAFT)
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .6Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .7Special Handling Instructions for FBGA Package ..9Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 9Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Ordering Information . . . . . . . . . . . . . . . . . . . . . .10Standard Products ................................................10Device Bus Operations . . . . . . . . . . . . . . . . . . . . .11
Table 1. Am29LV800B Device Bus Operations ..........11
DQ3: Sector Erase Timer .....................................24
Table 2. Write Operation Status ..................................25
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 26Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 26DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27CMOS Compatible ...............................................27
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents).......................................... 28Figure 10. Typical ICC1 vs. Frequency........................ 28Figure 11. Test Setup.................................................. 29Table 3. Test Specifications ........................................29
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Word/Byte Configuration ......................................11Requirements for Reading Array Data .................11Writing Commands/Command Sequences ..........11Program and Erase Operation Status ..................12Standby Mode ......................................................12Automatic Sleep Mode .........................................12RESET#: Hardware Reset Pin .............................12Output Disable Mode ............................................12
Table 2. Am29LV800BT Top Boot Block
Sector Addresses ........................................................13Table 3. Am29LV800BB Bottom Boot Block
Sector Addresses ........................................................13
Key to Switching Waveforms. . . . . . . . . . . . . . . . 29
Figure 12. Input Waveforms and
Measurement Levels................................................... 29
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30Read Operations ..................................................30
Figure 13. Read Operations Timings.......................... 30
Hardware Reset (RESET#) ..................................31
Figure 14. RESET# Timings........................................ 31
Word/Byte Configuration (BYTE#) .....................32
Figure 15. BYTE# Timings for Read Operations......... 32Figure 16. BYTE# Timings for Write Operations......... 32
Autoselect Mode ...................................................14
Table 4. Am29LV800B Autoselect Codes
(High Voltage Method) ................................................14
Erase/Program Operations ...................................33
Figure 17. Program Operation Timings....................... 34Figure 18. Chip/Sector Erase Operation Timings........ 35Figure 19. Data# Polling Timings (During
Embedded Algorithms)................................................ 36Figure 20. Toggle Bit Timings (During
Embedded Algorithms)................................................ 36Figure 21. DQ2 vs. DQ6.............................................. 37
Sector Protection/Unprotection ............................14Temporary Sector Unprotect ................................14
Figure 1. Temporary Sector Unprotect Operation....... 15Figure 2. In-System Sector Protect/
Sector Unprotect Algorithms....................................... 16
Hardware Data Protection ....................................17Command Definitions . . . . . . . . . . . . . . . . . . . . . 17Reading Array Data ..............................................17Reset Command ..................................................17Autoselect Command Sequence ..........................17Word/Byte Program Command Sequence ...........18
Figure 3. Program Operation...................................... 18
Temporary Sector Unprotect ................................37
Figure 22. Temporary Sector Unprotect
Timing Diagram........................................................... 37Figure 23. Sector Protect/Unprotect
Timing Diagram........................................................... 38
Alternate CE# Controlled Erase/Program Operations 39
Figure 24. Alternate CE# Controlled Write
Operation Timings....................................................... 40
Chip Erase Command Sequence .........................19Sector Erase Command Sequence ......................19Erase Suspend/Erase Resume Commands .........19
Figure 4. Erase Operation........................................... 20Table 1. Am29LV800B Command Definitions .............21
Write Operation Status . . . . . . . . . . . . . . . . . . . . 22DQ7: Data# Polling ...............................................22
Figure 5. Data# Polling Algorithm............................... 22
RY/BY#: Ready/Busy# .........................................22DQ6: Toggle Bit I ..................................................23DQ2: Toggle Bit II .................................................23Reading Toggle Bits DQ6/DQ2 ............................23DQ5: Exceeded Timing Limits ..............................23
Figure 6. Toggle Bit Algorithm..................................... 24
Erase and Programming Performance . . . . . . . 41Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 41TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 41Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 42TS 048—48-Pin Standard TSOP ........................42TSR048—48-Pin Reverse TSOP ........................43FBB 048—48-Ball Fine-Pitch Ball Grid Array
(FBGA) 6 x 9 mm ................................................44SO 044—44-Pin Small Outline Package .............45Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46
16/1/05
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PRELIMINARY (DRAFT)
6/1/052
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Am29LV800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
For new designs, S29AL008D supersedes Am29LV800B and is the factory-recommended migration path for this device. Please refer to the S29AL008D Family Datasheet for specifications and ordering information.
DISTINCTIVE CHARACTERISTICS
•Single power supply operation
—2.7 to 3.6 volt read and write operations for
battery-powered applications
•Embedded Algorithms
—Embedded Erase algorithm automatically
preprograms and erases the entire chip or any combination of designated sectors
—Embedded Program algorithm automatically
writes and verifies data at specified addresses
•Manufactured on 0.32 µm process technology
—Compatible with 0.5 µm Am29LV800 device
•High performance
—Access times as fast as 70 ns
•Minimum 1 million write cycle guarantee per sector•20-year data retention at 125°C
—Reliable operation for the life of the system
•Ultra low power consumption (typical values at 5 MHz)
————
200 nA Automatic Sleep mode current200 nA standby mode current7 mA read current
15 mA program/e+5rase current
•Package option
————
48-ball FBGA48-pin TSOP44-pin SO
Known Good Die (KGD)
(see publication number 21536)
•Flexible sector architecture
—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen Kbyte sectors (byte mode)
—One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)—Supports full chip erase—Sector Protection features:
•Compatibility with JEDEC standards
—Pinout and software compatible with single-power supply Flash
—Superior inadvertent write protection
•Data# Polling and toggle bits
—Provides a software method of detecting
program or erase operation completion
A hardware method of locking a sector to prevent any program or erase operations within that sectorSectors can be locked in-system or via programming equipment
Temporary Sector Unprotect feature allows code changes in previously locked sectors•Unlock Bypass Program Command
—Reduces overall programming time when
issuing multiple program command sequences
•Ready/Busy# pin (RY/BY#)
—Provides a hardware method of detecting
program or erase cycle completion
•Erase Suspend/Erase Resume
—Suspends an erase operation to read data from,
or program data to, a sector that is not being erased, then resumes the erase operation
•Top or bottom boot block configurations available
•Hardware reset pin (RESET#)
—Hardware method to reset the device to reading
array data
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21490Rev: GAmendment/+5 Issue Date: May 25, 2005
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GENERAL DESCRIPTION
The Am29LV800B is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The device is also available in Known Good Die (KGD) form. For more information, refer to publication number 21536. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0 volt VCC supply to perform read, program, and erase operations. A stan-dard EPROM programmer can also be used to program and erase the device.
This device is manufactured using AMD’s 0.32 µm process technology, and offers all the features and benefits of the Am29LV800, which was manufactured using 0.5 µm process technology. In addition, the Am29LV800B features unlock bypass programming and in-system sector protection/unprotection.The standard device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus conten-tion the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Reg-ister contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algo-rithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that auto-matically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6
After a program or erase cycle (toggle) status bits.
has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.Hardware data protection measures include a low VCC detector that automatically inhibits write opera-tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via pro-gramming equipment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any opera-tion in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system micropro-cessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective-ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tun-neling. The data is programmed using hot electron injection.
4Am29LV800B
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TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .6Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .7Special Handling Instructions for FBGA Package ..9Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 9Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Ordering Information . . . . . . . . . . . . . . . . . . . . . .10Standard Products ................................................10Device Bus Operations . . . . . . . . . . . . . . . . . . . . .11
Table 1. Am29LV800B Device Bus Operations ..........11
DQ3: Sector Erase Timer .....................................24
Table 2. Write Operation Status ..................................25
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 26Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 26DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27CMOS Compatible ...............................................27
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents).......................................... 28Figure 10. Typical ICC1 vs. Frequency........................ 28Figure 11. Test Setup.................................................. 29Table 3. Test Specifications ........................................29
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Word/Byte Configuration ......................................11Requirements for Reading Array Data .................11Writing Commands/Command Sequences ..........11Program and Erase Operation Status ..................12Standby Mode ......................................................12Automatic Sleep Mode .........................................12RESET#: Hardware Reset Pin .............................12Output Disable Mode ............................................12
Table 2. Am29LV800BT Top Boot Block
Sector Addresses ........................................................13Table 3. Am29LV800BB Bottom Boot Block
Sector Addresses ........................................................13
Key to Switching Waveforms. . . . . . . . . . . . . . . . 29
Figure 12. Input Waveforms and
Measurement Levels................................................... 29
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30Read Operations ..................................................30
Figure 13. Read Operations Timings.......................... 30
Hardware Reset (RESET#) ..................................31
Figure 14. RESET# Timings........................................ 31
Word/Byte Configuration (BYTE#) .....................32
Figure 15. BYTE# Timings for Read Operations......... 32Figure 16. BYTE# Timings for Write Operations......... 32
Autoselect Mode ...................................................14
Table 4. Am29LV800B Autoselect Codes
(High Voltage Method) ................................................14
Erase/Program Operations ...................................33
Figure 17. Program Operation Timings....................... 34Figure 18. Chip/Sector Erase Operation Timings........ 35Figure 19. Data# Polling Timings (During
Embedded Algorithms)................................................ 36Figure 20. Toggle Bit Timings (During
Embedded Algorithms)................................................ 36Figure 21. DQ2 vs. DQ6.............................................. 37
Sector Protection/Unprotection ............................14Temporary Sector Unprotect ................................14
Figure 1. Temporary Sector Unprotect Operation....... 15Figure 2. In-System Sector Protect/
Sector Unprotect Algorithms....................................... 16
Hardware Data Protection ....................................17Command Definitions . . . . . . . . . . . . . . . . . . . . . 17Reading Array Data ..............................................17Reset Command ..................................................17Autoselect Command Sequence ..........................17Word/Byte Program Command Sequence ...........18
Figure 3. Program Operation...................................... 18
Temporary Sector Unprotect ................................37
Figure 22. Temporary Sector Unprotect
Timing Diagram........................................................... 37Figure 23. Sector Protect/Unprotect
Timing Diagram........................................................... 38
Alternate CE# Controlled Erase/Program Operations 39
Figure 24. Alternate CE# Controlled Write
Operation Timings....................................................... 40
Chip Erase Command Sequence .........................19Sector Erase Command Sequence ......................19Erase Suspend/Erase Resume Commands .........19
Figure 4. Erase Operation........................................... 20Table 1. Am29LV800B Command Definitions .............21
Write Operation Status . . . . . . . . . . . . . . . . . . . . 22DQ7: Data# Polling ...............................................22
Figure 5. Data# Polling Algorithm............................... 22
RY/BY#: Ready/Busy# .........................................22DQ6: Toggle Bit I ..................................................23DQ2: Toggle Bit II .................................................23Reading Toggle Bits DQ6/DQ2 ............................23DQ5: Exceeded Timing Limits ..............................23
Figure 6. Toggle Bit Algorithm..................................... 24
Erase and Programming Performance . . . . . . . 41Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 41TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 41Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 42TS 048—48-Pin Standard TSOP ........................42TSR048—48-Pin Reverse TSOP ........................43FBB 048—48-Ball Fine-Pitch Ball Grid Array
(FBGA) 6 x 9 mm ................................................44SO 044—44-Pin Small Outline Package .............45Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46
Am29LV800B5
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PRODUCT SELECTOR GUIDE
Family Part NumberSpeed Options
Full Voltage Range: VCC = 2.7–3.6 V
707030
-70
909035
Am29LV800B
-90
12012050
-120
Max access time, ns (tACC)Max CE# access time, ns (tCE)Max OE# access time, ns (tOE)
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
VCCVSSRESET#
RY/BY#
Sector SwitchesErase VoltageGenerator
Input/Output
BuffersDQ0–DQ15 (A-1)
WE#BYTE#
StateControlCommandRegister
PGM VoltageGenerator
Chip EnableOutput Enable
Logic
STB
DataLatch
CE#OE#
STB
VCC Detector
Timer
Address LatchY-DecoderY-Gating
X-Decoder
Cell Matrix
A0–A18
6Am29LV800B
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CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for more information.
A15A14A13A12A11A10A9A8NCNCWE#RESET#NCNCRY/BY#A18A17A7A6A5A4A3A2A112345671011121314151617181920212223244847454443424140393837363534333231302928272625A16BYTE#VSSDQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4VCCDQ11DQ3DQ10DQ2DQ9DQ1DQ8DQ0OE#VSSCE#A0Standard TSOPA16BYTE#VSSDQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4VCCDQ11DQ3DQ10DQ2DQ9DQ1DQ8DQ0OE#VSSCE#A01234567101112131415161718192021222324Reverse TSOP4847454443424140393837363534333231302928272625A15A14A13A12A11A10A9A8NCNCWE#RESET#NCNCRY/BY#A18A17A7A6A5A4A3A2A121490G-1Am29LV800B7
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CONNECTION DIAGRAMS
This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for more information.
RY/BY#A18A17A7A6A5A4A3A2A1A0CE#VSSOE#DQ0DQ8DQ1DQ9DQ2DQ10DQ3DQ11123456710111213141516171819202122SO44434241403938373635343332313029282726252423RESET#WE#A8A9A10A11A12A13A14A15A16BYTE#VSSDQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4VCCFBGATop View, Balls Facing DownA6A13A5A9A4WE#A3RY/BY#A2A7A1A3B6A12B5A8B4RESET#B3NCB2A17B1A4C6A14C5A10C4NCC3A18C2A6C1A2D6A15D5A11D4NCD3NCD2A5D1A1E6A16E5DQ7E4DQ5E3DQ2E2DQ0E1A0F6BYTE#F5DQ14F4DQ12F3DQ10F2DQ8F1CE#G6DQ15/A-1G5DQ13G4VCCG3DQ11G2DQ9G1OE#H6VSSH5DQ6H4DQ4H3DQ3H2DQ1H1VSS8Am29LV800B
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Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory prod-ucts in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro-mised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
PIN CONFIGURATION
A0–A18
=19 addresses
DQ0–DQ14=15 data inputs/outputs
DQ15/A-1=DQ15 (data input/output, word
mode),
A-1 (LSB address input, byte mode)BYTE#CE#OE#WE#RESET#RY/BY#VCC
=Selects 8-bit or 16-bit mode=Chip enable= Output enable=Write enable
=Hardware reset pin, active low= Ready/Busy# output
=3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)=Device ground
NC=Pin not connected internally
LOGIC SYMBOL
19
A0–A18
DQ0–DQ15
(A-1)
CE#OE#WE#RESET#BYTE#
RY/BY#
16 or 8
VSS
Am29LV800B9
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ORDERING INFORMATIONStandard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Com-bination) is formed by a combination of the elements below.
Am29LV800B
T
-70
E
C
TEMPERATURE RANGEC=Commercial (0°C to +70°C)D=Commercial (0°C to +70°C) with Pb-free packageI = Industrial (–40°C to +85°C)F = Industrial (–40°C to +85°C) with Pb-free packageE =Extended (–55°C to +125°C)K =Extended (–55°C to +125°C) with Pb-free package
PACKAGE TYPEE=48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)F=48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)S=44-Pin Small Outline Package (SO 044)WB=48-Ball Fine Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 6 x 9 mm package (FBB048)
This device is also available in Known Good Die (KGD) form. See publication number 21536 for more information.
SPEED OPTION
See Product Selector Guide and Valid CombinationsBOOT CODE SECTOR ARCHITECTURET= Top sectorB= Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29LV800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program, and Erase
Valid Combinations for TSOP and SO Packages
AM29LV800BT-70, AM29LV800BB-70AM29LV800BT-90, AM29LV800BB-90AM29LV800BT-120, AM29LV800BB-120
EC, EI, FC, FI, SC, SI,
ED, EF, SD, SFEC, EI, EE, ED, EF
FC, FI, FE,
SC, SI, SE, SD, SF, EK, SK
Valid Combinations for FBGA PackagesOrder Number
AM29LV800BT-70, AM29LV800BB-70AM29LV800BT-90, AM29LV800BB-90AM29LV800BT-120, AM29LV800BB-120
WBC,WBD,WBI,WBFWBC, WBI,WBD,WBF,WBK,WBE
Package Marking
L800BT70V, L800BB70VL800BT90V, L800BB90VL800BT12V, L800BB12V
C, D,I, F
C, I,D, FK, E
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
10Am29LV800B
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DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command reg-ister itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The
contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1. Am29LV800B Device Bus Operations
DQ8–DQ15
Operation
ReadWriteStandbyOutput DisableReset
Sector Protect (Note 2)
CE#LLVCC ± 0.3 VLXL
OE#LHXHXH
WE#HLXHXL
RESET#
HHVCC ± 0.3 VHLVID
Addresses(Note 1)
AINAINXXX
Sector Address, A6 = L, A1 = H,
A0 = LSector Address, A6 = H, A1 = H,
A0 = L
AIN
DQ0–DQ7DOUTDINHigh-ZHigh-ZHigh-ZDIN
BYTE#= VIHDOUTDINHigh-ZHigh-ZHigh-ZX
BYTE# = VIL
DQ8–DQ14 = High-Z,
DQ15 = A-1
High-ZHigh-ZHigh-ZX
Sector Unprotect (Note 2)Temporary Sector Unprotect
LX
HX
LX
VIDVID
DINDIN
XDIN
XHigh-Z
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1.Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).
2.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configu-ration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifica-tions and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information.
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The device features an Unlock Bypass mode to facil-itate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence”section has details on programming data to the device using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-tors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions”section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode”and “Autoselect Command Sequence” sections for more information.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specifica-tion tables and timing diagrams for write operations.
In the DC Characteristics table, ICC3 and ICC4 repre-sents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is indepen-dent of the CE#, WE#, and OE# control signals. Stan-dard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset cir-cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algo-rithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase opera-tion is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or program-ming, the device draws active current until the operation is completed.
Output Disable Mode
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When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
Table 2. Am29LV800BT Top Boot Block Sector Addresses
Sector Size(Kbytes/Kwords)
/32/32/32/32/32/32/32/32/32/32/32/32/32/32/3232/168/48/416/8
Address Range (in hexadecimal)(x8)
Address Range00000h–0FFFFh10000h–1FFFFh20000h–2FFFFh30000h–3FFFFh40000h–4FFFFh50000h–5FFFFh60000h–6FFFFh70000h–7FFFFh80000h–8FFFFh90000h–9FFFFhA0000h–AFFFFhB0000h–BFFFFhC0000h–CFFFFhD0000h–DFFFFhE0000h–EFFFFhF0000h–F7FFFhF8000h–F9FFFhFA000h–FBFFFhFC000h–FFFFFh
(x16)
Address Range00000h–07FFFh08000h–0FFFFh10000h–17FFFh18000h–1FFFFh20000h–27FFFh28000h–2FFFFh30000h–37FFFh38000h–3FFFFh40000h–47FFFh48000h–4FFFFh50000h–57FFFh58000h–5FFFFh60000h–67FFFh68000h–6FFFFh70000h–77FFFh78000h–7BFFFh7C000h–7CFFFh7D000h–7DFFFh7E000h–7FFFFh
SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10SA11SA12SA13SA14SA15SA16SA17SA18
A180000000011111111111
A170000111100001111111
A160011001100110011111
A150101010101010101111
A14XXXXXXXXXXXXXXX0111
A13XXXXXXXXXXXXXXXX001
A12XXXXXXXXXXXXXXXX01X
Table 3. Am29LV800BB Bottom Boot Block Sector Addresses
Sector Size(Kbytes/Kwords)
16/88/48/432/16/32/32/32/32/32/32/32/32/32/32/32/32/32/32/32
Address Range (in hexadecimal)(x8)
Address Range00000h–03FFFh04000h–05FFFh06000h–07FFFh08000h–0FFFFh10000h–1FFFFh20000h–2FFFFh30000h–3FFFFh40000h–4FFFFh50000h–5FFFFh60000h–6FFFFh70000h–7FFFFh80000h–8FFFFh90000h–9FFFFhA0000h–AFFFFhB0000h–BFFFFhC0000h–CFFFFhD0000h–DFFFFhE0000h–EFFFFhF0000h–FFFFFh
(x16)
Address Range00000h–01FFFh02000h–02FFFh03000h–03FFFh04000h–07FFFh08000h–0FFFFh10000h–17FFFh18000h–1FFFFh20000h–27FFFh28000h–2FFFFh30000h–37FFFh38000h–3FFFFh40000h–47FFFh48000h–4FFFFh50000h–57FFFh58000h–5FFFFh60000h–67FFFh68000h–6FFFFh70000h–77FFFh78000h–7FFFFh
SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10SA11SA12SA13SA14SA15SA16SA17SA18
A180000000000011111111
A170000000111100001111
A160000011001100110011
A150000101010101010101
A140001XXXXXXXXXXXXXXX
A13011XXXXXXXXXXXXXXXX
A12X01XXXXXXXXXXXXXXXX
Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section.
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Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verifica-tion, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be pro-grammed with its corresponding programming algo-rithm. However, the autoselect codes can also be accessed in-system through the command register.When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in
Table 4. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0.To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 1. This method does not require VID. See “Command Definitions” for details on using the autoselect mode.
Table 4. Am29LV800B Autoselect Codes (High Voltage Method)
A18A11to to
WE#A12A10HHHHH
X
X
VID
X
L
X
L
H
X
X
VID
X
L
X
L
H
X
X
A8toA7X
A5toA2X
DQ8toDQ15X22hX22hXX
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L
X
DQ7toDQ001hDAhDAh5Bh5Bh01h (protected)00h (unprotected
)
DescriptionModeCE#LLLLL
OE#LLLLL
A9VID
A6L
A1L
A0L
Manufacturer ID: AMDDevice ID: Am29LV800B (Top Boot Block)Device ID: Am29LV800B (Bottom Boot Block)
WordByteWordByte
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.
The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details.
It is possible to determine whether a sector is pro-tected or unprotected. See “Autoselect Mode” for details.
Sector Protection/unprotection can be implemented via two methods.
The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algo-rithms and Figure 23 shows the timing diagram. This method uses standard microprocessor bus cycle
timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unpro-tect write cycle.
The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Publication number 20536 contains further details; contact an AMD representative to request a copy.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly pro-tected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algo-rithm, and Figure 22 shows the timing diagrams, for this feature.
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START
RESET# = VID
(Note 1)Perform Erase orProgram Operations
RESET# = VIH
Temporary SectorUnprotect Completed
(Note 2)
Notes:
1.All protected sectors unprotected.
2.All previously protected sectors are protected once
again.
Figure 1. Temporary Sector Unprotect Operation
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STARTPLSCNT = 1RESET# = VIDWait 1 msProtect all sectors:The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect addressSTARTPLSCNT = 1RESET# = VIDWait 1 msTemporary SectorUnprotect ModeNoFirst Write Cycle = 60h?YesSet up sectoraddressNoFirst Write Cycle = 60h?YesAll sectorsprotected?YesSet up first sectoraddressNoTemporary SectorUnprotect ModeSector Protect:Write 60h to sectoraddress withA6 = 0, A1 = 1, A0 = 0Wait 150 μsVerify Sector Protect: Write 40h to sector addresswith A6 = 0, A1 = 1, A0 = 0Sector Unprotect:Write 60h to sectoraddress withA6 = 1, A1 = 1, A0 = 0ResetPLSCNT = 1IncrementPLSCNTWait 15 msVerify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0Read from sector addresswith A6 = 0, A1 = 1, A0 = 0NoNoPLSCNT= 25?Data = 01h?IncrementPLSCNTYesYesRead from sector addresswith A6 = 1, A1 = 1, A0 = 0NoYesNoData = 00h?YesSet upnext sectoraddressDevice failedProtect anothersector?NoRemove VID from RESET#PLSCNT= 1000?YesDevice failedWrite reset commandSector UnprotectAlgorithmLast sectorverified?YesRemove VID from RESET#NoSector ProtectAlgorithmSector ProtectcompleteWrite reset commandSector UnprotectcompleteFigure 2. In-System Sector Protect/
Sector Unprotect Algorithms
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Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 1 for command definitions). In addition, the following hardware data protection measures prevent acci-dental erasure or programming, which might other-wise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
prevent unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automat-ically reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing dia-grams in the “AC Characteristics” section.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.
The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the opera-tion is complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase opera-tion, writing the reset command returns the device to reading array data (also applies during Erase Sus-pend).
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more infor-mation on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more infor-mation. The Read Operations table provides the read parameters, and Figure 13 shows the timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is pro-tected. Table 1 shows the address and data require-ments. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect
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command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufac-turer code. A read cycle at address XX01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Tables 2 and 3 for valid sector addresses.
The system must write the reset command to exit the autoselect mode and return to reading array data.
sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Addi-tional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 1 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.
Figure 3 illustrates the algorithm for the program operation. See the Erase/Program Operations table in “AC Characteristics” for parameters, and to Figure 17for timing diagrams.
Word/Byte Program Command Sequence
The system may program the device by word or byte, depending on the state of the BYTE# pin. Program-ming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com-mand. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 1 shows the address and data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the pro-gramming operation. The program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity.Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.
STARTWrite ProgramCommand SequenceEmbeddedProgramalgorithm in progressData Poll from SystemVerify Data?NoYesIncrement AddressNoLast Address?YesProgramming CompletedUnlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command
Note: See Table 1 for program command sequence.
Figure 3. Program Operation
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Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and veri-fies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these opera-tions. Table 1 shows the address and data require-ments for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.
Figure 4 illustrates the algorithm for the erase opera-tion. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to Figure 18 for timing diagrams.
between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data.The system must rewrite the command sequence and any additional sector addresses and commands.The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com-mands are ignored. Note that a hardware resetduring the sector erase operation immediately termi-nates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integ-rity.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to “Write Operation Status”for information on these status bits.
Figure 4 illustrates the algorithm for the erase opera-tion. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to Figure 18 for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 1 shows the address and data requirements for the sector erase command sequence.
The device does not require the system to prepro-gram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to elec-trical erase. The system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algo-rithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase opera-tion. Addresses are “don’t-cares” when writing the Erase Suspend command.
When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and sus-pends the erase operation.
After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command defini-tions apply. Reading at any address within erase-sus-pended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together,
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to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for informa-tion on these status bits.
After an erase-suspended program operation is com-plete, the system can once again read array data within non-suspended sectors. The system can deter-mine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information.
The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information.
The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase opera-tion. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.
Notes:
1.See Table 1 for erase command sequence.
2.See “DQ3: Sector Erase Timer” for more information.
STARTWrite Erase Command SequenceData Poll from SystemEmbedded Erasealgorithmin progressNoData = FFh?YesErasure CompletedFigure 4. Erase Operation
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Table 1. Am29LV800B Command Definitions
Bus Cycles (Notes 2-5)
CommandSequence(Note 1)
Read (Note 6)Reset (Note 7)
Manufacturer IDAutoselect (Note 8)Device ID, Top Boot Block Device ID,
Bottom Boot BlockSector Protect Verify (Note 9)
WordByteWordByteWordByteWord
4
ByteWordByteWordByte43
AAA555AAA555AAAXXXXXX555AAA555AAAXXXXXX
AAAAA090AAAAB030
CyclesFirstAddrRAXXX555AAA555AAA555AAA555
AA
5552AA5552AA555PAXXX2AA5552AA5555555PD005555
555AAA555AAA8080
555AAA555AAAAAAA
2AA5552AA5555555
555AAASA
1030
DataRDF0AAAAAA
2AA5552AA5552AA5552AA
55
AAA555AAA555AAAA020
555555
555AAA555AAA555AAA555
90909090
X00X01X02X01X02(SA)X02(SA)X04PA
0122DADA225B5BXX00XX010001PD
Second Addr
Data
Third Addr
Data
Fourth Addr
Data
Fifth Dat
Addra
Sixth Addr
Dat
a
11444
ProgramUnlock Bypass
Unlock Bypass Program (Note 10)2Unlock Bypass Reset (Note 11)Chip EraseSector Erase
Erase Suspend (Note 12)Erase Resume (Note 13)
WordByteWordByte26611
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18–A12 uniquely select any sector.
Notes:
1.See Table 1 for description of bus operations.2.All values are in hexadecimal.
3.Except when reading array or autoselect data, all bus cycles are write operations.4.Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
5.Address bits A18–A11 are don’t cares for unlock and command cycles, unless PA or SA required.6.No unlock or command cycles required when reading array data.
7.The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status data).8.The fourth cycle of the autoselect command sequence is a read cycle.
9.The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more
information.10.The Unlock Bypass command is required prior to the Unlock Bypass Program command.
11.The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass
mode.12.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase operation.13.The Erase Resume command is valid only during the Erase Suspend mode.
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WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 2 and the following subsec-tions describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for deter-mining whether a program or erase operation is com-plete or in progress. These three bits are discussed first.
STARTRead DQ7–DQ0Addr = VADQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum pro-grammed to DQ7. This DQ7 status also applies to pro-gramming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading array data.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to “1”; prior to this, the device outputs the “complement,” or “0.” The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7–DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. Figure 19, Data# Polling Timings (During Embedded Algorithms), in the “AC Characteristics”section illustrates this.
Table 2 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm.
Notes:
1.VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address.2.DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
DQ7 = Data?YesNoNoDQ5 = 1?YesRead DQ7–DQ0Addr = VADQ7 = Data?YesNoFAILPASSFigure 5. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC.
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If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode.
Table 2 shows the outputs for RY/BY#. Figures 13, 14, 17 and 18 shows RY/BY# for read, reset, program, and erase operations, respectively.
Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for era-sure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus-pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era-sure. Thus, both status bits are required for sector and mode information. Refer to Table 2 to compare outputs for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the “DQ6: Toggle Bit I” sub-section. Figure 20 shows the toggle bit timing dia-gram. Figure 21 shows the differences between DQ2 and DQ6 in graphical form.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or com-plete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are pro-tected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to deter-mine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alterna-tively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.
Table 2 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm. Figure 20 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit II”.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-ever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typi-cally, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not tog-gling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog-gling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully com-pleted the program or erase operation. If it is still tog-gling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the opera-tion (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended.
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The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the opera-tion has exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the reset command to return the device to reading array data.
STARTRead DQ7–DQ0(Note Read DQ7–DQ0DQ3: Sector Erase Timer
Toggle Bit = Toggle?YesNoNoDQ5 = 1?After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from “0” to “1.” The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 µs. See also the “Sector Erase Command Sequence” section.
After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0”, the device will accept addi-tional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 2 shows the outputs for DQ3.
YesRead DQ7–DQ0Twice(Notes 1, 2)Toggle Bit = Toggle?NoYesProgram/EraseOperation Not Complete, Write Reset CommandProgram/EraseOperation CompleteNotes:
1.Read toggle bit twice to determine whether or not it is
toggling. See text.2.Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 6. Toggle Bit Algorithm
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Table 2. Write Operation Status
Operation
Standard Embedded Program AlgorithmModeEmbedded Erase AlgorithmErase Suspend Mode
Reading within Erase Suspended Sector
Reading within Non-Erase
Suspended SectorErase-Suspend-Program
DQ7(Note 2)DQ7#01DataDQ7#
DQ6ToggleToggleNo toggleDataToggle
DQ5(Note 1)
000Data0
DQ3N/A1N/ADataN/A
DQ2(Note 2)No toggleToggleToggleDataN/A
RY/BY#
00110
Notes:
1.DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.2.DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further de-tails.
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages. . . . . . . . . . . . . .–65°C to +150°CAmbient Temperature
with Power Applied. . . . . . . . . . . .–65°C to +125°COutput Short Circuit Current (Note 3). . . . .200 mANotes:
Voltage with Respect to Ground
. . . . . . . . . . . . . . . .VCC (Note 1)–0.5 V to +4.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . .A9, OE#, and RESET# (Note 2). . . . . . . . . . . .–0.5 V to +12.5 V . . . . . . All other pins (Note 1)–0.5 V to VCC+0.5 V
1.Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to –
2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8.2.Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5 V. During voltage transitions, A9, OE#, and RESET# may
undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.3.No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one
second.Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA). . . . . . . . .0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA). . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA). . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for regulated voltage range. . +3.0 V to +3.6 VVCC for full voltage range . . . . . . +2.7 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
20 ns
+0.8 V–0.5 V–2.0 V
20 ns
VCC +2.0 VVCC +0.5 V2.0 V
20 ns
20 ns
20 ns
20 ns
Figure 7. Maximum Negative Overshoot
WaveformFigure 8. Maximum Positive Overshoot
Waveform
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DC CHARACTERISTICSCMOS Compatible
Parameter
ILIILITILO
Description
Input Load CurrentA9 Input Load CurrentOutput Leakage Current
Test Conditions
VIN = VSS to VCC, VCC = VCC max
VCC = VCC max; A9 = 12.5 VVOUT = VSS to VCC, VCC = VCC max
CE# = VIL, OE# = VIH, Byte Mode
CE# = VIL, OE# = VIH, Word Mode
CE# = VIL, OE# = VIHCE#, RESET# = VCC±0.3 VRESET# = VSS ± 0.3 VVIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V
–0.50.7 x VCC
VCC = 3.3 V
IOL = 4.0 mA, VCC = VCC min IOH = –2.0 mA, VCC = VCC min IOH = –100 µA, VCC = VCC min
0.85 VCCVCC–0.42.3
2.5
V
11.5
5 MHz1 MHz5 MHz1 MHz
7272150.20.20.2
Min
Typ
Max±1.035±1.0124124305550.8VCC + 0.312.50.45
mAµAµAµAVVVVVmAUnitµAµAµA
ICC1
VCC Active Read Current (Notes 1, 2)
ICC2ICC3ICC4ICC5VILVIHVIDVOLVOH1VOH2VLKO
VCC Active Write Current (Notes 2, 3, 5)
VCC Standby Current (Note 2)VCC Reset Current (Note 2)Automatic Sleep Mode (Notes 2, 4)Input Low VoltageInput High Voltage
Voltage for Autoselect and Temporary Sector UnprotectOutput Low VoltageOutput High Voltage
Low VCC Lock-Out Voltage (Note 4)
Notes:
1.The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.2.Maximum ICC specifications are tested with VCC = VCCmax.
3.ICC active while Embedded Erase or Embedded Program is in progress.
4.Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.5.Not 100% tested.
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DC CHARACTERISTICS (Continued)Zero Power Flash
20Supply Current in mA15
10
5
0
0
500
1000
1500
2000Time in ns
Note: Addresses are switching at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
2500300035004000
10
8Supply Current in mA3.6 V
6
2.7 V
4
2
01
2
3
Frequency in MHz
Note: T = 25 °C
Figure 10. Typical ICC1 vs. Frequency
45
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TEST CONDITIONS
3.3
2.7 kΩ
Table 3. Test Specifications
Test Condition
-70
-90,-1201 TTL gate 30
50.0–3.01.5 1.5
100
pFnsVVVUnit
DeviceUnderTest
CL
6.2 kΩ
Output Load
Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall TimesInput Pulse Levels
Input timing measurement reference levels
Note: Diodes are IN30 or equivalent
Figure 11. Test Setup
Output timing measurement reference levels
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
Steady
Changing from H to LChanging from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
OUTPUTS
3.0 V0.0 VInput1.5 VMeasurement Level1.5 VOutputFigure 12. Input Waveforms and
Measurement Levels
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AC CHARACTERISTICSRead Operations
ParameterJEDECtAVAVtAVQVtELQVtGLQVtEHQZtGHQZ
StdtRCtACCtCEtOEtDFtDFtOEH
Description
Read Cycle Time (Note 1)Address to Output DelayChip Enable to Output DelayOutput Enable to Output DelayChip Enable to Output High Z (Note 1)Output Enable to Output High Z (Note 1)Output Enable Hold Time (Note 1)
Read
Toggle and Data# Polling
CE# = VILOE# = VILOE# = VIL
Test Setup
MinMaxMaxMaxMaxMaxMinMinMin
Speed Options-70707070302525
-909090903530300100
-120120120120503030
Unitnsnsnsnsnsnsnsnsns
tAXQXtOH
Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1)
Notes:
1.Not 100% tested.
2.See Figure 11 and Table 3 for test specifications.
tRCAddressesCE#tOtOEHWEOutputsRESET#RY/BY#0 VFigure 13. Read Operations Timings
Addresses StabletACCtDOE#tCEHIGH ZOutput ValidtOHIGH Z30Am29LV800B
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AC CHARACTERISTICSHardware Reset (RESET#)
ParameterJEDEC
StdtREADYtREADYtRPtRHtRPDtRB
Description
RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note)RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note)RESET# Pulse Width
RESET# High Time Before Read (See Note)RESET# Low to Standby ModeRY/BY# Recovery Time
Test Setup
MaxMaxMinMinMinMin
All Speed Options
2050050050200
Unitµsnsnsnsµsns
Note: Not 100% tested.
RY/BY#CE#, OE#tRHRESET#tRPtReadyReset Timings NOT during Embedded AlgorithmsReset Timings during Embedded AlgorithmstReadyRY/BY#tRBCE#, OE#RESET#tRP
Figure 14. RESET# Timings
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AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
StdtELFL/tELFHtFLQZtFHQV
Description
CE# to BYTE# Switching Low or HighBYTE# Switching Low to Output HIGH ZBYTE# Switching High to Output Active
MaxMax Min
2570 -70
Speed Options
-9053090
30120-120
Unitnsnsns
CE#
OE#
BYTE#
tELFL
BYTE# Switching from word
to byte mode
DQ0–DQ14
Data Output(DQ0–DQ14)Data Output
DQ15/A-1
DQ15OutputtFLQZ
tELFH
AddressInput
BYTE#
BYTE# Switching from byte to word mode
DQ0–DQ14
Data OutputAddressInputtFHQ
V
Data Output(DQ0–DQ14)DQ15Output
DQ15/A-1
Figure 15. BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET (tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 16. BYTE# Timings for Write Operations
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AC CHARACTERISTICSErase/Program Operations
ParameterJEDECtAVAVtAVWLtWLAXtDVWHtWHDX
StdtWCtAStAHtDStDHtOES
tGHWLtELWLtWHEHtWLWHtWHWLtWHWH1tWHWH2
tGHWLtCStCHtWPtWPHtWHWH1tWHWH2tVCStRBtBUSY
Description
Write Cycle Time (Note 1)Address Setup TimeAddress Hold TimeData Setup TimeData Hold Time
Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low)CE# Setup TimeCE# Hold TimeWrite Pulse WidthWrite Pulse Width High
Programming Operation (Note 2)Sector Erase Operation (Note 2)VCC Setup Time (Note 1)Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
ByteWord
MinMinMinMinMinMinMinMinMinMinMinTypTypTypMinMinMin
354535 -7070
Speed Options
-9090045450000035309110.750090
505050-120120
Unitnsnsnsnsnsnsnsnsnsnsnsµssecµsnsns
Notes:
1.Not 100% tested.
2.See the “Erase and Programming Performance” section for more information.
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AC CHARACTERISTICS
Program Command Sequence (last two cycles)tWCAddresses555htASPAtAHCE#OE#tWWE#tCStDDatatDPDtBUSYRY/BY#StatuDOUTtRBtWPHtWHWH1PAPARead Status Data (last two cycles)tCA0hVCCtVCSNotes:
1.PA = program address, PD = program data, DOUT is the true data at the program address.2.Illustration shows device in word mode.
Figure 17. Program Operation Timings
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AC CHARACTERISTICS
Erase Command Sequence (last two cycles)tWCAddresses2AAhtASSA555h for chip erasetACE#VAVARead Status DataOE#tWWE#tCStDtCtWPtWHWHtDData55h30h10 for Chip ErasetBUSYRY/BY#tVCVCCtRBInProgressCompleteNotes:
1.SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).2.Illustration shows device in word mode.
Figure 18. Chip/Sector Erase Operation Timings
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AC CHARACTERISTICS
tRCdressesVAtACCCE#tCHOE#tOEHWE#tOHDQ7ComplementComplemeTruValid DataHigh tDFtCEVAVAtOEQ0–DQ6tBUSRY/BY#Status Status TruValid DataHigh Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
ead cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
tRCAddressesVAtACCCE#tCHOE#tOEHWE#tOHDQ6/DQ2tBUSRY/BY#High Valid (first read)Valid (second read)Valid (stops toggling)Valid DatatDFtCEVAVAVAtOENote: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
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AC CHARACTERISTICS
EnterEmbeddedErasing
WE#
EraseSuspendEraseEnter EraseSuspend Program
EraseSuspendProgram
EraseResume
Erase Suspend
Read
Erase
EraseComplete
Erase SuspendRead
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 21. DQ2 vs. DQ6
Temporary Sector Unprotect
ParameterJEDEC
StdtVIDRtRSP
Description
VID Rise and Fall Time (See Note)
RESET# Setup Time for Temporary Sector Unprotect
MinMin
All Speed Options
5004
Unitnsµs
Note: Not 100% tested.
12 VRESET#0 or 3 VtVIDRProgram or Erase Command SequencetVIDR0 or 3 VCE#WE#tRSPRY/BY#
Figure 22. Temporary Sector Unprotect
Timing Diagram
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AC CHARACTERISTICS
VIDVIHRESET#SA, A6,A1, A0Valid*Sector Protect/UnprotectValid*Verify40hValid*Data60h60hStatus1 μsCE#Sector Protect: 150 μsSector Unprotect: 15 msWE#OE#* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23. Sector Protect/Unprotect
Timing Diagram
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AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
ParameterJEDECtAVAVtAVELtELAXtDVEHtEHDX
StdtWCtAStAHtDStDHtOES
tGHELtWLELtEHWHtELEHtEHELtWHWH1tWHWH2
tGHELtWStWHtCPtCPHtWHWH1tWHWH2
Description
Write Cycle Time (Note 1)Address Setup TimeAddress Hold TimeData Setup TimeData Hold Time
Output Enable Setup Time
Read Recovery Time Before Write (OE# High to WE# Low)WE# Setup TimeWE# Hold TimeCE# Pulse WidthCE# Pulse Width HighProgramming Operation (Note 2)
Sector Erase Operation (Note 2)
ByteWord
MinMinMinMinMinMinMinMinMinMinMinTypTypTyp
354535-7070
Speed Options
-9090045450000035309110.7
505050-120120
Unitnsnsnsnsnsnsnsnsnsnsnsµssec
Notes:
1.Not 100% tested.
2.See the “Erase and Programming Performance” section for more information.
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AC CHARACTERISTICS
PA for program555 for program2AA for erase SA for sector erase555 for chip erase AddressestWCtWHWE#tGHELOE#tCPCE#tWStCPHtDtDDatatRA0 for programPD for program55 for erase 30 for sector erase10 for chip erase DQ7DOUTData# PollingPAtAStAHtWHWH1 or tBUSRESET#RY/BY#Notes:
1.PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written
to the device. 2.Figure indicates the last two bus cycles of command sequence.3.Word mode address used as an example.
Figure 24. Alternate CE# Controlled Write Operation Timings
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ERASE AND PROGRAMMING PERFORMANCE
ParameterSector Erase TimeChip Erase Time Byte Programming TimeWord Programming TimeChip Programming Time(Note 3)
Byte ModeWord Mode
Typ (Note
1)
0.71491195.8
300360 2717
Max (Note 2)
15
Unitssµsµsss
Excludes system level overhead (Note 5)
Comments
Excludes 00h programming prior to erasure
Notes:
1.Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.2.Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3.The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.4.In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5.System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 1 for further information on command definitions.6.The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#)
Input voltage with respect to VSS on all I/O pinsVCC Current
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
Min–1.0 V–1.0 V–100 mA
Max12.5 VVCC + 1.0 V+100 mA
TSOP AND SO PIN CAPACITANCE
Parameter Symbol
CINCOUTCIN2
Parameter Description
Input CapacitanceOutput CapacitanceControl Pin Capacitance
Test SetupVIN = 0VOUT = 0VIN = 0
Typ68.57.5
Max7.5129
UnitpFpFpF
Notes:
1.Sampled, not 100% tested.
2.Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Minimum Pattern Data Retention Time
Test Conditions
150°C125°C
Min1020
UnitYearsYears
Am29LV800B41
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PHYSICAL DIMENSIONS*TS 048—48-Pin Standard TSOP
Dwg rev AA; 10/99* For reference only. BSC is an ANSI standard for Basic Space Centering.
42Am29LV800B
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PHYSICAL DIMENSIONSTSR048—48-Pin Reverse TSOP
Dwg rev AA; 10/99* For reference only. BSC is an ANSI standard for Basic Space Centering.
Am29LV800B43
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PHYSICAL DIMENSIONS
FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm
Dwg rev AF; 10/9944Am29LV800B
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PHYSICAL DIMENSIONS
SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/9945Am29LV800B
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REVISION SUMMARYRevision E (January 1998)
Distinctive Characteristics
Changed typical read and program/erase current specifications.
Device now has a guaranteed minimum endurance of 1,000,000 write cycles.
In Note 2, the worst case endurance is now 1 million cycles.
Revision F (January 1999)
Global
Changed references for process technology to “0.32 µm.”
Replaced the 70R ns regulated voltage speed option with 70 ns full voltage speed option.
In-System Sector Protect/Unprotect Algorithm Figure
Corrected A6 to 0, Changed wait specification to 150 µs on sector protect and 15 ms on sector unprotect.
Distinctive Characteristics
Added 20-year data retention bullet.
Connection Diagrams
Reverse TSOP: Modified markings.
FBGA: Replaced Bump side (bottom) view with top view.
DC Characteristics
Changed typical read and program/erase current specifications.
AC Characteristics
Alternate CE# Controlled Erase/Program Operations:Changed tCP to 35 ns for 70R, 80, and 90 speed options.
Ordering Information
Valid Combinations for FBGA Packages: New Table.
DC Characteristics—CMOS Compatible
ICC1, ICC2, ICC3, ICC4, ICC5: Added Note 2 “Maximum ICC specifications are tested with VCC = VCCmax”.ICC3, ICC4: Deleted VCC = VCCmax.
Erase and Programming Performance
Device now has a guaranteed minimum endurance of 1,000,000 write cycles.
Physical Dimensions
Corrected dimensions for package length and width in FBGA illustration (standalone data sheet version).
Physical Dimensions
Changed package drawing to FBB048.
Revision F+1 (February 1999)
Physical Dimensions
Corrected ball grid layout on FBB048 drawing. Added “048” to drawing title.
Revision E+1 (March 1998)
In-System Sector Protect/Unprotect Algorithms Figure
In the sector protect algorithm, added a “Reset PLSCNT=1” box in the path from “Protect another sector?” back to setting up the next sector address.
Revision F+2 (February 1999)
Distinctive Characteristics, Operating Ranges
Corrected to indicate that the VCC voltage range for all devices is 2.7–3.6 V.
DC Characteristics
Changed Note 1 to indicate that OE# is at VIH for the listed current.
AC Characteristics
Erase/Program Operations; Alternate CE# Controlled Erase/Program Operations: Corrected the notes reference for tWHWH1 and tWHWH2. These parametersare 100% tested. Corrected the note reference for tVCS. This parameter is not 100% tested.
Revision F+3 (July 2, 1999)
Global
Added references to availability of device in Known Good Die (KGD) form.
Revision F+4 (July 26, 1999)
Global
Added the 70R speed option, which is available in the extended temperature range.
Temporary Sector Unprotect Table
Added note reference for tVIDR. This parameter is not 100% tested.
Figure 23, Sector Protect/Unprotect Timing Diagram
A valid address is not required for the first write cycle; only the data 60h.
Erase and Programming Performance
Ordering Information
Deleted the extended temperature range from the FBGA valid combinations.
Revision G (November 10, 1999)
Ordering Information
Deleted commercial and industrial temperature ranges from the 70R speed option.
Am29LV800B46
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AC Characteristics—Figure 17. Program Operations Timing and Figure 18. Chip/Sector Erase Operations
Deleted tGHWL and changed OE# waveform to start at high.
Revision G+3 (June 4, 2004)
Ordering Information
Added Lead-free (Pb-free) options to the Tempera-ture range breakout of the OPN table and to the Valid Combinations table.
Physical Dimensions
Replaced figures with more detailed illustrations.
Revision G+4 (January 20, 2005)
Added migration statement to cover page and first page of data sheet.Added Colophon.Updated Trademark
Revision G+1 (July 7, 2000)
Ordering Information
Inserted dashes into ordering part numbers. Deleted burn-in option.
Revision G+2 (August 14, 2000)
Global
Deleted 70R and 80 ns speed options and burn-in option.
Revision G+5 (May 25, 2005)
Updated migration statement on cover page and first page of data sheet.Updated trademarks.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies
47Am29LV800B
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